This standard specifies the principle, instrument and materials, sample preparation, measurement steps and data processing for determining the net carrier concentration in silicon epitaxial layers using the voltage-capacitance relationship of gated and non-gated diodes. This standard applies to n-type or p-type epitaxial layers on substrates of the same or opposite conductivity type with an epitaxial layer thickness not less than a certain minimum thickness value (see Appendix B), and also applies to bulk materials. GB/T 14863-1993 Standard method for determining the net carrier concentration in silicon epitaxial layers using the voltage-capacitance relationship of gated and non-gated diodes GB/T14863-1993 Standard download decompression password: www.bzxz.net

National Standard of the People's Republic of China
Standard test method for net carrier density in silicon epitaxial layers by voltage-capacitance of galed and ungated diodes1 Subject content and scope of application
GB/T 14863—93
This standard specifies the principle, instrument and materials for determining the net carrier concentration in silicon epitaxial layers by voltage-capacitance of galed and ungated diodes, sample preparation, measurement procedures and data processing. This standard is applicable to n-type or β-type epitaxial layers on substrates of the same or opposite conductivity type with an epitaxial layer thickness not less than a certain minimum thickness value (see Appendix B), and is applicable to bulk materials. 2 Reference Standards
SJ1550 Determination of resistivity of silicon epitaxial layer by three-probe breakdown voltage method 3 Terminology
3.1 Breakdown voltage
Reverse bias when the diode under test has a leakage current of 10 μA. 4 Method Principle
4.1 Measure the small signal high frequency capacitance of gated or non-gate-controlled Pn junction or Schottky diode as a function of reverse bias voltage, and determine the net carrier concentration as a function of depth from the measured capacitance and reverse bias value. For the measurement of gate-controlled diodes, a constant bias is applied to the gate. 5 Instruments and MaterialsbzxZ.net
5.1 Capacitance bridge or capacitance meter
Full scale range is 1 to 1 000 pF, increased or decreased by ten times. The measurement frequency range is 0. 09 to 1. 1 MHz, and the accuracy of each range is better than 1.0% of full scale, and the repeatability is better than 0.25% of full scale. The instrument shall be able to withstand an external DC bias of ±200V or higher, compensate for the stray capacitance of the external probe holder of not less than 5pF, and have an internal AC measurement signal not greater than 0.05V (rm$). 5.2 Digital voltmeter or potentiometer
with a sensitivity better than 1mV, an accuracy better than 0.5% of full scale, and a repeatability better than 0.25% of full scale. The input impedance shall be not less than 100 mA, and the common mode rejection ratio shall be greater than 100 dB at 50 Hz. 5.3 The DC power supply
shall be continuously adjustable and provide a DC output of 0 to ±200V (open circuit) with a ripple less than 1%. 5.4 The curve plotter
shall be able to monitor the forward and reverse IV characteristics of the diode. The curve plotter can add up to 200V at 0.1mA in the reverse direction and 1.1V at 1mA in the forward direction, and the sensitivity is better than 10A/division. 5.5 Standard capacitors
At the measurement frequency, the accuracy is better than 0.25%, one capacitor should be in the range of 1~10pF, and the other capacitor should be in the range of 10~100pF.
5.6 Precision voltage source
Can provide 0~～200V output voltage, and its accuracy should be better than 0.1% of the output voltage. 5.7 Probe holder
Fix the diode sample, so that the probe can form ohmic contact with the diffusion region or barrier region, epitaxial layer and the gate of the gate-controlled diode, and can prevent the diode from being exposed to light when measuring the disk. A vacuum fixture should be available. For the inverse epitaxial layer, the positive surface contact is used, while for the isotype epitaxial layer, the vacuum chuck is used to make electrical contact with the substrate. 5.8 The tool microscope, projector or planimeter can measure the junction diameter with an accuracy better than 0.5%; or measure the junction area with an accuracy better than 1.0%. 5.9 Shielded cable
Establish electrical connection between the probe station, power supply, capacitance bridge or capacitance meter, and digital voltmeter or potentiometer. 5.10 DC voltage source
Continuously switchable, with an output voltage range of 0 to 40V, and a DC output ripple of no more than 1% (this source is not required for measuring non-gated diodes).
6 Sample preparation
6.1: According to whether the conductivity type of the epitaxial layer and the substrate is the same or opposite, use Appendix A (Supplement) A1 or A2 to measure the thickness of the epitaxial layer; estimate the carrier concentration of the epitaxial layer to be measured. 6.2 Fabricate a gated or non-gate-controlled diode on the epitaxial layer to be tested (refer to Appendix D for sample structure), the area of ​​its active region is 5×10-*~5×10cm (for a circular active region, this area corresponds to a diameter in the range of 0.025~~0.138cm). 6.3 Prepare a junction diode, the surface carrier concentration of which is at least 100 times that of the epitaxial layer, and the junction depth is less than 1.5um. The junction depth is measured and recorded in accordance with Appendix A (Supplement) A2, and the sheet resistance is measured and recorded in accordance with Appendix A (Supplement) A3 or other appropriate methods. The surface carrier concentration is determined and recorded from the sheet resistance and junction depth according to 5SJ1550. 6.4 Fabricate a gate-controlled diode so that the gate overlaps the boundary of the junction region or Schottky contact region. The gate breakdown voltage VGB>20V. 6.5 If Method B (see 7-9.1) is used, a MOS capacitor should also be fabricated on the undiffused epitaxial region to determine the gate bias voltage of the gate-controlled diode.
7 Measurement Procedure
7.1 Calibration of Measuring Instruments.
7.7.1 To measure standard capacitance, connect a shielded cable of appropriate length to a capacitance bridge or meter. Zero the capacitance bridge or meter with only the cable connected and no standard capacitors. 7.1.2 Connect the cable to a standard capacitor, measure and record the capacitance (pF). Then remove the capacitor. 7.1.3 Connect the cable to another standard capacitor, measure and record the capacitance (pF). Then remove the capacitor. 7.1.4 Check the performance of a digital voltmeter or potentiometer in the 1 to 200 V range by measuring five or more voltages from a precision voltage source within this voltage range.
7.1.5 If the capacitance or voltage measuring instrument does not meet the required indicators (see 5.1 and 5.2 for the values), it is necessary to make necessary adjustments according to the corresponding instrument manual so that the instrument meets the required indicators before measuring the sample. 7.2 Depending on the type of measuring instrument used, measure and record the active device area (cm\) to an accuracy of 1%, or measure and record the device diameter (cm) to an accuracy of 0.5%.
7.3 Place the sample on the probe station and connect the probe station to the epitaxial layer as close to the source area as possible (for substrates of the same conductive type, the connection of the epitaxial layer is led out from the substrate)
GB/T 14863--93
7.4 When using the probe to make an electrical connection with the barrier region or diffusion region of the diode, care should be taken to avoid penetrating the diffusion layer of the shallow diffusion diode due to excessive probe pressure, causing a short circuit or excessive leakage current. 7.5 Connect the probe station and the tracer with a shielded cable (see 5.4). 7.6 Under 1V forward bias, measure the forward resistance R(2) of the diode as follows. 7.6.1 Measure and record the diode current at 0.9V forward bias, mA. 7.6.2 Measure and record the diode current at 1.1V forward bias, mA. 7.6.3 Calculate and record the value of R as follows:
R = 200/(I - I)
Where: 1:—Current at 1.1V forward bias, mA1I1—Current at 0.9V forward bias, mA. (1
7.6.4 Because R values ​​equal to or greater than 200 will introduce measurement errors in some capacitance measuring instruments. In order to make the forward resistance of the sample less than 2000, it is necessary to use alloy, diffusion or gold-plated electrical contacts. 7.7 Use the same: grapher to apply reverse bias to the test diode, measure and record the breakdown voltage V (V) (see 8.1). Do not touch the probe when applying bias.
7.8 Reduce the voltage applied to the probe to zero and lift the probe to disconnect it from the barrier or diffusion layer. If measuring a non-gated diode, follow step 7.9.
7.8.1 If you want to measure a gated diode, lower the probe to contact the gate. Use the grapher to apply between the gate and the epitaxial layer. Voltage + (V+20)V and - (V+20)V. Check if the current value at both voltages is less than 10μA. If the current is equal to or less than 10μA, the voltage of the tracer will be zero and measure according to step 7.9. If the current is greater than 10μA, select another diode on the epitaxial wafer and repeat the procedure from 7.2.
7.8.2 If gate breakdown occurs during operation 7.8.1, reduce the tracer voltage to zero. Then lower the probe to a spare diode. Gradually increase the voltage of the tracer between the gate and the epitaxial layer and record the voltage value when the gate breakdown occurs. Use this method to measure more than three diodes, calculate and record the average breakdown voltage (V) as the typical gate breakdown voltage VGBe7.9 Disconnect the shielded cable between the probe and tracer. If measuring a non-gated diode, proceed to step 7.10. 7.9.1 If measuring a gated diode, use method A or B to determine the appropriate gate bias. Method A is generally used. When higher accuracy is required, use method B.
7.9.1.1 Method A: Use a gate bias of +20 V for the n-type epitaxial layer and a gate bias of -20 V for the p-type epitaxial layer. If gate breakdown occurs at a voltage less than 20 V, do not use this method. 7.9.1.2 Method B: Use a MOS capacitor made on an epitaxial wafer to measure the flat-band voltage. Use the flat-band voltage as the gate bias. 7.10 Connect a shielded cable between the probe station and a capacitance bridge or penetration meter so that the lower end of the bridge or capacitance meter is connected to the epitaxial layer or substrate (see 7.3) and the upper end is connected to the probe that contacts the barrier or diffusion region. If measuring a non-gated diode, proceed to step 7.11. 7.10.1 If measuring a gated diode, use another shielded cable to connect the power supply (see 5.10) and the probe that contacts the gate - lower the probe to contact the gate and apply the appropriate gate bias between the gate probe and ground as determined in 7.9.1. In any case, the cable should be kept as short as possible. In the case of a defective gate, a series resistor can be used as a current limiter. In this case, a 0.1 uF capacitor is connected between the gate and ground to ensure that the gate is AC grounded. 7.11. The zeroing method of the capacitance bridge or capacitance meter is as follows: 7.11.1 Apply a rated 1V reverse bias, set the capacitance bridge or capacitance meter to the least sensitive range, and slowly lower the probe so that it just contacts the barrier or diffusion area of ​​the diode being tested. The contact point is determined by the forward deflection of the capacitance bridge or capacitance meter. 7.11.2 Select the most sensitive range of the capacitance bridge or capacitance meter to indicate no more than full scale. 7.11.3 Raise the probe so that it just breaks electrical contact with the barrier or diffusion region. 7.11.4 Adjust the capacitance bridge or capacitance meter so that it indicates zero in the selected range (within the accuracy of the instrument). GB/T14863-93
7.12 Lower the probe to contact the barrier or diffusion region. Apply a specified 1 V reverse bias to the diode under test and measure its capacitance (pF). The applied voltage and measured capacitance (each value should not be less than three significant figures) are recorded in the data table (see Appendix C) as V, and C, respectively. The voltage and capacitance values ​​of each subsequent time should also be recorded in the table. Table 7.1 shows the format of the sample data table used for the incremental method (8.3.1), and Table 7.2 shows the format of the sample data table used for the curve fitting method (8.3.2). Although reverse bias is involved, all voltages are considered positive. 7.13 Adjust the voltage to obtain a new capacitance value that is 4% to 6% lower than the previous capacitance value. The voltage and capacitance value (each value is not less than three significant figures) are recorded in the data table as V, and (z), respectively. Do not touch the probe when the bias is applied. 7.14 Repeat the steps described in 7.13 to reduce the capacitance by 1% to 6% until the breakdown voltage is reached or the capacitance value begins to increase with the increase of reverse bias. Measure the gate-controlled diode, and the gate cannot withstand the potential of (V + 20)V in 7.8.1, then stop the measurement when the voltage is not greater than (V|-|V|-5). Where V is the gate breakdown voltage measured in 7.8.2, and V is 7.9, 1.1 or the applied gate bias determined in 7.9.1.2, with 5 V being a safety margin to prevent gate breakdown. When the measurement procedure is completed, reduce all biases to zero, raise the probe, and remove the sample from the probe table. For the incremental method, at least four data points should be used, and for the curve fitting method, the number of data points should be consistent with the order of the expected fit. 8 Calculation
8.1 If the diode diameter is measured in 7.2 instead of the diode area, calculate the diode area (cm*) as follows: A 0. 7B5 4d2
Where: A-——diode area, cm\
d——diameter, cm.
B.2 Peripheral correction, if the diode being measured is made using a planar diffusion (as opposed to a table) process Pn For each measured capacitance C, perform the following calculations, subtract the capacitance of the surrounding edge from the measured capacitance, and record the result. Follow the steps described in 8.3.
8-2.1 Calculate and record the estimated value of the depletion layer width X (cm) using the following relationship: X, = 1. 040 4(A/C,)
The ith measured capacitance, pF.
Where: C,
8.2.2 Calculate and record the estimated value of the ith peripheral capacitance C, (pF) corresponding to the measured capacitance, using the following relationship: 5.7931A17u
C= InL(1 + Xo/X)/(1+4x.(3.54 9AV2 + 4X))Where: X,-
Junction depth, cm (see 6. 3).
8.2.3 Using the following relationship, calculate and record the corrected estimate of electrocorrosion CspF)Ca = C, — CH
8.2.4 Using the following relationship, calculate and record the new estimate of the depletion layer width X,(cm): X, = 1.040 4(A/C.)
B.2.5 Using the following relationship, calculate and record the difference between the old and new depletion layer width estimates Xz(cm): X, = (X1 - X.)/X,
8. 2. 6 Compare the value of X. with 0.000 1; (3)
++-.---+.-(6)
GB/T 14863—93
8.2.6.1 If X,=0.000 1, then 8. 2. 3 8.2.6.2 If X2 is 20.0001, set X = X1, and then calculate and record a new estimate of the depletion layer width and peripheral capacitance according to 8.2.2 to 8.2.6. Repeat 8.2.2 to 8.2.6 until the conditions of 8.2.6 are met. 8.3 Calculation of carrier concentration profile
8.3.1 Incremental method
8.3.1.1 Calculate S using the following relationship; from 1 to 1-3, and record in the data table (see Table C1), where n is the number of capacitance-voltage data pairs measured above:
S,=In[(Vi++ 0.6)/(V:+ 0.6)J/An[C./C+s] Where: V.--the i-th recorded voltage, V; V.+--the i+3-th recorded voltage, V
The first capacitance record value corrected for peripheral capacitance as required (see 8.2), PF The i+3-th corrected capacitance record value·PF. 8.3.1.2 Calculate and record in the data table the depth W corresponding to each capacitance value C, using the following relationship: W, = 10 404(A/C,)
8.3.1.3 Calculate and record in the data table the average depth W, i from 1 to 3; r(Ws)\ -(w.)\,u,-n
w\, = [s(w.,-w]
8.3.1.4 Calculate and record in the data table the carrier density N, corresponding to each average depth W, using the following relationship: N, = 6.193 × 10\w(ww)
Vi+$ - V.
8.3.1.5 Calculate the true depth W\ for each W, value plus the junction depth and record it in the data table. 8.3.2 Curve Fitting Method
8.3.2.1 Fit a polynomial function of the following form to the data: 1/Ce* - a, +a,, +a0?++*
Where: C---the first capacitance value calculated according to the fit, pF, A...at
(9)
(12)
For all: values, the coefficient value C determined when the expression (C-C)\ is the minimum, corrected by the surrounding capacitance as required (see 8.2),
uV,+0.600,V: is the voltage measurement value recorded, V represents the order of the polynomial, for all 1 values, the selected value represents the lowest order fit for [(C,-C,)/C.|≤0.01, R≤π-1; where is the number of points of the measured capacitance-voltage data. 8.3.2-2 Record the values ​​of C, and agm1*a in the data table (see Table C2). 8.3.2.3 Calculate 8.3.2.1 using the following relationship The derivative D of the polynomial in the equation is recorded in the data table; D, = at + 2ai +.-kau*-!
Note that if a polynomial with an order higher than 3 is used, errors may occur in the calculated carrier density. 8.3.2.4 Calculate the carrier concentration corresponding to each depletion layer width using the following relationship and record it in the data table. (13)
9 Report
9.1 The report should include the following:
9. 1. 1 Operator.
Date of measurement.
GB/T 14863-93
W; = 10 404(A/C.)
N,=(-1.19985×10°)/A3D
Batch number, wafer and diode sampling plan (if applicable). Sample number and type.
Diode manufacturing process and whether it is gated or non-gate-controlled. Junction depth of diffused diode, μm.
Forward resistance of the diode, 0.
Area of ​​the diode, cm.
Gate bias of the gate-controlled diode, V.
Calculation method used.
List the data in the data table shown in Table C1 (incremental method) or Table C2 (curve fitting method). Calculated carrier density, cm
10Method precision
10.1 For samples with carrier concentrations below 1×10 cm-\, specify three depths for measurement, which are selected in a relatively flat portion of the distribution. For two samples with carrier concentrations greater than 1×101°cm-\, specify two depths for measurement. Based on preliminary analysis of seven samples measured each day on three days in six laboratories, the precision (2) ranges from 4.6% to 17.4%. Statistical data are listed in Appendix E. GB/T 14863—93
Appendix A
Referenced foreign standards
(supplement)
A1ASTMF95\Measurement of the thickness of silicon epitaxial layer on the same type of substrate by infrared reflection methodA2ASTMF1101Measurement of the thickness of silicon epitaxial layer or diffusion layer by angle grinding and dyeing technologyMeasurement of the sheet resistance of silicon epitaxial layer, diffusion layer and ion implantation layer by linear four-probe method3ASTMF374\
Note: 1) Cited from SEMI Standard Volume 6, the translation is published by China Standards Press. Appendix B
Relationship curve between carrier concentration and depletion degree (supplement)
B1 Relationship curve between carrier concentration and depletion width of silicon single-sided abrupt junction 10'E
Figure B1 Relationship between depletion region width and reverse bias voltage under single-sided abrupt junction approximation (silicon, 300°K) Appendix C
Data record decay
(supplement)
Incremental method table
Table C1 Experimental data table of incremental method
Operator
Diode manufacturing process
Junction depth, um
Forward resistance, 2
Sampling scheme
Gate voltage, V
Non-gated
Diode area, cm\
Curve fitting method table
Operator
Diode manufacturing process
Junction depth um
Forward resistance, n
Diode area, cm
GB/T14863—93
Experimental data table of curve fitting method
Sampling scheme
Non-gated
Gate voltage, V
Schematic diagram of gated pn junction
(reference)
D1 An example of gated Pn junction of n-type epitaxial layer is shown in Figure D1. am
Fitting coefficient
N diffusion region of front contact
GB/T 1486393
Lead diffusion layer connection
Diffusion
Epitaxial layer
Gold contact on the back
Oxide
Figure D1 Surface diagram of the pn junction made on the n-type epitaxial layer. Note: (I) The aluminum gate is isolated from the epitaxial layer and overlaps with the diffusion area or the injection area. ② In order to make the back contact with the epitaxial layer, evaporated gold is in contact with the back. ③ In order to make the front contact with the epitaxial layer, there is a metallized n+ diffusion area around the diffusion area or the injection area. Appendix E
Cyclic test data
(reference)
Data on the CV cycle test accuracy of planar diodes E1
Sample number
Number of thin mothers,
Average carrier concentration expressed in 10\boron atoms/cm. Standard error value expressed in 10" atoms/cm2. The standard error value expressed as a percentage of the average ion gain. Sample No.
GB/T14863-93
Additional Notes:
This standard was proposed by the Ministry of Machinery and Electronics Industry of the People's Republic of China. This standard was drafted by the 46th and 4th Institutes of the Ministry of Machinery and Electronics Industry. The main drafters of this standard are Sun Yizhi, Zhang Ruoyu, Xie Chongmu and Han Yanfen.And overlap with the diffusion area or injection area. ② In order to make the back side contact with the epitaxial layer, the evaporated gold forms contact with the back side. ③ In order to make the front side contact with the epitaxial layer, there is a metallized n+ diffusion area around the diffusion area or injection area. Appendix E
Cyclic test data
(reference)
Data of planar diode CV cycle test accuracy E1
Sample number
Number of thin mother,
Average carrier concentration expressed in 10\ boron atoms/cm2. Standard error value expressed in 10" atoms/cm2. Standard error value expressed in percentage of average carrier acquisition. Sample number
GB/T14863-93
Additional notes:
This standard was proposed by the Ministry of Machinery and Electronics Industry of the People's Republic of China. This standard was drafted by the 46th and 4th institutes of the Ministry of Machinery and Electronics Industry. The main drafters of this standard are Sun Yizhi, Zhang Ruoyu, Xie Chongmu and Han Yanfen.And overlap with the diffusion area or injection area. ② In order to make the back side contact with the epitaxial layer, the evaporated gold forms contact with the back side. ③ In order to make the front side contact with the epitaxial layer, there is a metallized n+ diffusion area around the diffusion area or injection area. Appendix E
Cyclic test data
(reference)
Data of planar diode CV cycle test accuracy E1
Sample number
Number of thin mother,
Average carrier concentration expressed in 10\ boron atoms/cm2. Standard error value expressed in 10" atoms/cm2. Standard error value expressed in percentage of average carrier acquisition. Sample number
GB/T14863-93
Additional notes:
This standard was proposed by the Ministry of Machinery and Electronics Industry of the People's Republic of China. This standard was drafted by the 46th and 4th institutes of the Ministry of Machinery and Electronics Industry. The main drafters of this standard are Sun Yizhi, Zhang Ruoyu, Xie Chongmu and Han Yanfen.
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