This standard specifies four types of interfaces for transmitting synchronization reference signals 2048 kbit/s and k2048 kHz, as well as the performance specifications of network synchronization parameters and reference interfaces. This standard applies to the engineering design of digital synchronization networks and the maintenance and operation of digital synchronization networks. GB/T 15837-1995 Digital Synchronization Network Interface Requirements GB/T15837-1995 Standard download decompression password: www.bzxz.net

GB/T 15837-1995
This standard adopts the drift specifications in the ITU G.811 and G.823 recommendations in 1988 and the compatibility regulations of clocks at all levels in GB13158--91.
This standard is the first digital synchronization network interface requirement formulated for the digital synchronization network. It can ensure that the digital synchronization network works within the specified drift performance range.
To adapt to the development of various services in the digital network, this standard specifies four interface requirements and compatibility criteria between various levels in the reference distribution system. This standard should be revised with the development of digital synchronization networks. This standard is proposed and managed by the Telecommunications Transmission Research Institute of the Ministry of Posts and Telecommunications. The drafting unit of this standard: Telecommunications Transmission Research Institute of the Ministry of Posts and Telecommunications. Drafters of this standard: Wang Guozhen, Li Lin, Jin Guangxu, Cheng Genlan. 583www.bzxz.net
1 Scope
National Standard of the People's Republic of China
Digital Synchronization Network Interface Requirements
Synchronization interface requirments for digital networkGB/T 15837-1995
This standard specifies four types of interfaces for transmitting synchronization reference signals of 2048kbit/s and 2048kHz, as well as the performance specifications of synchronization parameters and reference interfaces within the network. (When the reference clock signal crosses two independent network nodes, this standard is still applicable) This standard applies to the engineering design of digital synchronization networks and the maintenance and operation of digital synchronization networks. 2 Referenced Standards
The provisions contained in the following standards constitute the provisions of this standard through reference in this standard. When this standard is published, the versions shown are valid. All standards are subject to revision, and parties using this standard should explore the possibility of using the latest versions of the following standards. GB12048--89 Requirements for clock and synchronization equipment in digital network ITUG.811:1988 Timing requirements for reference clock source output applicable to quasi-synchronous work of international digital links ITUG.823:1988 Control of jitter and drift in digital network based on 2048kbit/s series 3 Definitions
3.1 Reference clock source interface
Maintenance monitoring points should be provided at the output of the reference clock source. The input port, output port and related equipment interface of the reference clock source are defined as the reference clock source interface.
3.2 Reference clock signal interface
The interface that directly accepts the secondary (or tertiary, quaternary) clock control of the synchronization node is the reference clock signal interface, which is defined on the digital distribution frame (as shown in Figure 2).
3.3 Fast capture working mode of the clock
When the clock starts to lock to the external synchronization reference, a smaller time constant is used to make the local clock frequency track faster and approximate the frequency of the external reference signal.
3.4 ​​Free working mode of the clock
When the clock is not locked to the external synchronization reference, it does not use storage technology to maintain its frequency accuracy. 3.5 Holding working mode of the clock
When the external synchronization reference signal is lost, the clock does not lock to the external synchronization reference, but uses storage technology to maintain the known frequency accuracy of the last period of time before the external synchronization reference is lost, and maintains a certain frequency accuracy for a period of time. 3.6 Normal working mode of the clock
When the clock is locked to the external synchronization reference, it has the same long-term frequency average as the external synchronization reference. 3.7 Time interval error
The cumulative deviation of the effective instant of the measured digital signal from its ideal time position within a specified period of time. 3.8 Maximum Time Interval Error
Approved by the State Administration of Technical Supervision on December 13, 1995 584
Implementation on June 1, 1996
GB/T15837—1995
The maximum value of the time interval error (TIE) in all possible measurement intervals within a measurement period is defined as the maximum time interval error (MTIE), as shown in Figure 1. For example, the maximum value of △T in the measurement period S is the MTIE. Equivalent to the slope of the long-term rate deviation
Observe the current period S
Figure 1 Maximum Time Interval Error
3.9 Synchronous Node
Time t,s
The point in a synchronization network where timing information is derived, sent or received and processed for synchronization purposes. In a synchronization network, it is a switching device or an integrated timing supply system containing a clock.
3.10 Local Node
The node that directly interfaces with user equipment.
3.11 Pseudosynchronism
Two signals that appear at the same rate at corresponding valid instants and whose variations are limited to a specified range are called quasisynchronism.
3.12 Reference clock source
A device that provides a long-term frequency accuracy equal to or better than ±1×10-1 timing signal after verification with Coordinated Universal Time (UTC) is called a reference clock source. It serves as a reference for controlling other clocks in the network. The reference clock source can generate timing signals that are completely autonomous from other references. Another alternative is a non-autonomous reference clock source, that is, obtaining frequency and time services from a device directly controlled by Coordinated Universal Time (UTC).
3.13 Slip
The duplication and loss of bit groups in synchronous and quasi-synchronous networks due to the difference in the reading and writing time of the bit stream in the frame memory is called slip. 3.14 Timing jitter
The short-term variation of the effective instant of a digital signal from its ideal time position, where short-term variation means a jitter frequency greater than or equal to 10Hz. Timing jitter can cause crosstalk or distortion of the original analog signal and is the main cause of slippage at the input port of digital switching equipment. 3.15 Wander (i.e. drift)
The long-term change (10Hz) of the digital signal from its ideal position at its effective instant. Wander is mainly caused by the delay variation of the transmission medium and equipment, and also includes the damage of the synchronization reference system. Wander is also the main cause of slippage in the synchronization network. 585
4 Reference clock source requirements
4.1 Distribution diagram of reference clock
GB/T15837---1995
The reference clock source provides the highest quality base push signal for the network. The common point of the synchronization network is that the synchronization reference is distributed from one or more reference clock sources at the top of the timing link to the synchronization reference distribution system of the lowest layer node, as shown in Figure 2. When the synchronization reference clock is distributed from the reference clock source at the node through the transmission system and the intermediate clock, the phase stability of the reference gradually degrades.
Note: In practice, phase drift will accumulate in the distribution connection. The drift accumulation is determined by the drift generated by the clock, the drift generated by the transmission system and the drift transfer characteristics of the clock. If the drift characteristics are not properly standardized, the sliding performance indicators cannot be guaranteed. The reference clock source affects the performance of the entire network. The current technical level can provide excellent clock performance, and its drift value only accounts for a small part of the total drift of the entire network.
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1--reference clock source 2-reference clock source interface; 3-transmission system; 4-1, ear, NV type interface: defined on the digital distribution frame output by the synchronization node, 5-synchronization node Figure 2 Reference distribution diagram
4.2 Base push clock source requirements
4.2.1 Long-term frequency deviation
The long-term frequency deviation of the reference clock should be less than 1×10-11 or better than 1X10-11 (three days) after comparison with the coordinated universal time (UTC).
4.2.2 Phase discontinuity requirements of the reference clock source output In order to ensure the normal operation of the regenerative repeater and terminal equipment, the phase discontinuity of the reference clock source output port should be limited to no more than 1/8UI.
4.2.3 Maximum allowable drift requirements of the reference clock source output port The maximum allowable drift of the reference clock source output port is expressed in MTIE. Under normal operating conditions, the MTIE within the S second observation period should not exceed the following limits: (1) When 0.05
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