Some standard content:
Military Standard FL7035 of the Electronic Industry of the People's Republic of China
SJ 207061998
PCI Local Bus Specification
Published on March 18, 1998
Implemented on May 1, 1998
Approved by the Ministry of Electronics Industry of the People's Republic of China Foreword
PCI SIG Preface
Referenced Documents
Specification Content
Application of PCI Local Bus
3.4 Overview of PCI Local Bus
3.5 Features and Advantages of PCI Local Bus
Signal Definition
Signal Type Definition
Pin Function Group
System Pin
Address and Data Pins
Interface Control Pin
Arbitration Pin (Only for Bus Master)| |tt||Error reporting pin
Interrupt pin (optional)
Cache memory support pin (optional)Additional signals
4.2.9 64-bit bus expansion pin (optional)4.2.10 TAG/boundary scan pin (optional)4.3 Sideband signals
4.4 Central resource function
5 Bus operation
KAoNrKAca-
5.1. Bus Commands
5.1.1 Command Definition
5.1.2 Command Usage Rules
5.2 Basic Principles of PCI Protocol
Basic Transfer Control
Byte Alignment
Bus Driver and Conversion
Transaction Order
Combination, Merging, Folding
Bus Transaction
Read Transaction
Write Transaction
Transaction Termination
Arbitration Signal Protocol
Fast Back-to-Back Transaction
Arbitration Parking
Self-Standard Device Delay
Master Device Data Delay
Arbitration Delay
Inter-Exclusive Access
Start of Inter-Exclusive Access
Continuation of Inter-Exclusive Access|| tt||5.6.3 Access to Lock Agents ·
Completion of Mutually Exclusive Access
5.6.5 Support for Lock# and Write-Back Cache Coherency Full Bus Lock
5.7 Other Bus Operations
Device Select
Special Cycles
Address/Data Stepping
Configuration Cycles
Interrupt Acknowledgement
Error Functions
Parity Check
Error Reporting
Cache Support
Definition of Cache States
Supported State Transitions
Timing Diagrams
Write-Through Cache Support
Arbitration Notes
64-Bit Bus Extensions
PCI 64-bit addressing
5.11 Special design considerations
Electrical specifications
15V and 3.3V translation paths
Dynamic and static driver specifications
6.2 Component specifications
5V signal environment
3.3V signal environment
Timing specifications
6.2.4 Improper input and metastability
Specifications for vendor-provided information
Pinout recommendations
KAoNrKAca-
(103)
6.3 System (motherboard) specifications
Clock skew
System timing budget||tt ||Physical Requirements
Connector Pinout
Expansion Board Specifications
Board Pinout
Power Requirements
Physical Requirements
Mechanical Specifications
7.2 Expansion Card Physical Dimensions and Tolerances
Physical Description of Connectors
Plane Board Implementation
Configuration Space
Organization of Configuration Space
Functions of Configuration Space…
Device Identification
Device Control
Device Status
Other Functions
Base Address
8.3 PCI Expansion ROM
8.3.1 Contents of the PCI Expansion ROM
8.3.2 Power-On Self-Test (POST) Procedure
8.3.3 PC-Compatible Expansion ROM
Vital Product Data (VPD)
Importance of the VPD
Location of the VPD
VPD Data Structure
Format of the VPD
VPD Example
Device Driver,
System Reset
User-Defined Configuration Items
PCF Definitions
PCF Example
966MHzPCI Technical Specifications
Device Implementation Considerations·
Configuration Space
Proxy Structure
66MHz Enable (M66EN) Pin Definition
Electrical Specifications
66MHzPCI Path Transition Diagram.
Signal Environment
Timing Specifications
Vendor-Provided Specifications
System (Plane) Specifications
iiKAoNrKAca-
(205)
(205)
(206)）
(209 ）
Clock uncertainty
Pull-up resistor
System timing arrangement
Physical requirements
Connector pin assignment
Add-on board specifications
Appendix A
Special periodic message (supplement)
State machine (supplement)
Appendix B
Operation rules (supplement)
Appendix C
Appendix D
Classification code (supplement)
Appendix E System transaction sequence (supplement) Appendix F Terminology (reference)
This specification is based on the "PCI Local Bus Specification 2.1" (1995) issued by PCISIG (Special Interest Group), and its technical content and writing rules are equivalent to it. The concept of PCI originated from Intel Corporation of the United States, and the full English name is: Peripheral Component Interconnect. PCISIG, established by Intel and many other companies in the world in 1991, is an international industry association for microcomputers. The main task of the association is to promote the development of PCI local bus industry standards. Today, PCISIG has about 500 member companies. Nine companies elected by voting form the PCISIG Steering Committee, which is responsible for managing the business of SIG and supervising various suggestions for revising PCI specifications. The PCI Local Bus Specification 1.0 formulated by PCISIG was publicly released in 1992. After revision, version 2.0 was released in 1993, and version 2.1 was released in 1995, and it was implemented on June 1, 1995. PCI local bus is the interconnection mechanism between the processor/memory and peripheral controller components and peripheral add-on boards on microcomputer systems. PCI Local Bus Specification 2.1 specifies the protocol, electrical, mechanical and configuration space specifications of the interconnection mechanism, and also defines the signal environment using 5V and 3.3V in terms of electricity. PCI Local Bus Specification 2.1 is one of the industry standards generally followed by various microcomputer systems today. However, since the birth of the PC specification, no corresponding standards have been formulated in China. Rapidly converting these advanced international industry standards into my country's industry standards will help meet the needs of design, manufacturing and application of my country's microcomputer products. When formulating this specification based on the "PCI Local Bus Specification 2.1", in order to facilitate comparison, the preface of the original international industry standard was retained, and the preface, Chapter 1 Scope, and Chapter 2 Reference Documents were added. Therefore, the number of each chapter of the original international industry standard was increased by 2, that is, the original Chapter 1 became Chapter 3 of this specification, Chapter 2 became Chapter 4 of this specification, and so on. The article numbers and contents of each chapter remain unchanged. At the same time, the figure title numbers and table numbers that were numbered by chapter in the original international industry standard were changed to unified numbers. "PCI Local Bus Specification 2.1".1》The starting point of the architecture design lies in its openness, high bandwidth, long life cycle, reliability, suitable performance-price ratio, compatibility with the system add-on boards based on ISA, EISA or MC that are still widely used today, and the flexibility of continued use. For example: the 32-bit or 64-bit multiplexed address data lines specified in the bus specification and the burst working mode allowed effectively overcome the data bottleneck that is difficult to overcome by the traditional PC bus. When working at a main frequency of 33MHz, the bandwidth of the data path corresponding to 32-bit or 64-bit reaches 132MB/s or 264MB/s; when working at a main frequency of 66MHz, the bandwidth of the data path corresponding to 32-bit or 64-bit reaches 264MB/s or 528MB/s.
PCI Local Bus Specification 2.1》The design independent of the processor enables this bus specification to meet the needs of cross-platform applications. At the same time, the multi-master capability of the bus specification also allows any PCI master device to have equal access to any master device! Target device.
iiiKAoNiKAca
This specification supersedes earlier documents
PCI SIG Foreword
This document contains the formal specification of the protocol, electrical, and mechanical characteristics of the PCI Local Bus, version 2.1. As a revision, this document became effective on June 1, 1995, and supersedes the PCI Local Bus Specification, version 2.0, published on April 30, 1993.
Conventions in the document
The following names and conventions are used in this document: asserted, deasserted, edge, clock edge reserved
signal names
signal range
implementation notes The terms "asserted" and "deasserted" refer to the globally visible state of the signal at the arrival of the clock edge! Not to the transition of the signal.
The terms "edge" and "clock edge" refer to the rising edge of the clock. For the PCI bus, only the rising edge of the clock is significant for timing signals. A # sign at the end of a signal name indicates that the signal is active low. A # sign without the # sign indicates that the signal is active high.
"Reserved" refers to content or undefined status or information that is not defined at this time. No use of any reserved field in the PCI specification is allowed. All fields in the PCI specification can only be modified by the PCISIG through legal means. Use of any PCI reserved field will cause PCI incompatibility. Product functionality will not be guaranteed in the current specification or future versions of the PCI specification. Signal names are in bold. When you first mention a signal, write its full name and give its abbreviation in parentheses. When you mention the signal again, use its abbreviation.
The signal name is followed by a range enclosed in square brackets, for example, AD[31::00], which indicates a range of logically related signals. The first number in the square brackets represents the highest bit of the range, and the second number represents the lowest bit.
The implementation points are enclosed in a box. They are not part of the PCI specification and are only used to illustrate a problem or diagram.
1 Scope
PC Local Bus Specification for Military Standards of the Electronic Industry of the People's Republic of China
PCI Local bus specification
SJ20706--1998
This specification specifies the PCI local bus specification for microcomputer systems. It establishes a path for upgrading from this specification to future system requirements. The main contents include: the scope of the PCI local bus, referenced documents, signal definitions, bus operations, electrical specifications, mechanical specifications, configuration space, 66MHz PCI specifications, and appendices. This specification is applicable to PCI components and add-on board products of 32-bit or 64-bit microcomputer systems designed and manufactured with microprocessors from different manufacturers to meet mobile computing applications, desktop computing applications, and some server application platforms. 2 References
GB1988-89 Information Processing Information Interchange Seven-bit Coded Character Set GB/T4880-91 World Language Code
IEEE1149.1--1995 Standard Test Access Port and Boundary Scan Architecture EEE12751994 Boot (Initialization, Configuration) Software Core Requirements and Practices MIL-STD-1344--1995 Scheme A: Test Methods for Electronic Connectors IEEE1394-1995 High Performance Serial Bus (1394 Bus) 3 General
3.1 Specification Content
PCI Local Bus is a high-performance 32-bit or 64-bit bus with address and data multiplexing. The bus is used as an interconnection mechanism to connect highly integrated external control components, peripheral add-on boards and processor/memory systems.
PCI Local Bus Specification Version 2.1 contains protocols, electrical specifications, machine specifications and configuration specifications for PCI bus components and expansion boards. The electrical definition provides 5V and 3.3V signal environments. The PCI local bus specification defines the PCI component environment. If you need more signals, please contact PCISIG to obtain the "PCI Design Guide" and "PCI BIOS Specification". For information on how to join PCISIG or how to obtain these components, see Article 6 (3.6) of this chapter.
Released by the Ministry of Electronics Industry of the People's Republic of China on March 18, 1998
Implemented on May 1, 1998
3.2 Motivation
SJ 20706—1998
Graphics-oriented operating systems such as WDN DOWS and OS/2 have made the standard PCI/O structure a bottleneck between the processor and the display device. This bottleneck can be eliminated by moving high-bandwidth functions to the processor bus close to the system. When using the "local bus (iocalbus)" design, it is seen that the performance of graphical user interfaces (GUIs) and other high-bandwidth functions (such as full-screen animated video, SCSI, and networking) have all improved significantly.
The advantages of using the local bus design have led to the implementation of several revisions of the local bus. The benefits of using the local bus design have clearly shown that in the PC industry, an open standard system I/O bus has become clear, so it is very important and absolutely necessary to develop a new standard local bus to simplify the design, reduce costs, and increase the choice of local bus devices and add-in cards.
3.3 Application of PCI Local Bus
The PCI local bus has been developed with an initial goal. The goal is to establish an industry standard local bus architecture with high performance. This bus architecture provides low cost and allows for future modifications. The basic point is to establish a new performance price point in today's systems. It is important that the new standard can adapt to future system needs and can be applied in systems across multiple platforms and architectures. Figure 1 shows the various specifications of the PCI local bus.
Server
High-end desktop
Mid-range and low-end desktop
Mobile computing
64-bit upgrade path
Automatic configuration
X86 architecture
Processor series
Alpha AXP
Processor series
Figure 1 PCI local bus application
Future CPU
The PCI local bus can not only adapt to applications from low-end to high-end desktops, but also meet the needs of various mobile applications through department servers. The new standard fully estimates the 3.3V demand of the mobile environment and the upcoming desktop application from 5V to 3.3V is needed, the PCI local bus specifies two voltages and describes a clear migration path between them.
SJ 20706—1998
PCI components and add-on card interfaces are independent of the processor, allowing these components and cards to effectively switch to the next generation of processors using a multi-processor architecture. The independence from the processor enables the PCI local bus to optimize IO functions, allowing the local bus with the processor/memory subsystem to operate concurrently, thereby accommodating multiple high-performance peripherals, including graphics, animation video, LAN, SCSI, FDDI and hard disk drives. High-quality enhanced video and multimedia display (i.e. HDTV and 3D graphics) and other high-bandwidth IO will continue to require increased local bus bandwidth. The 32-bit data and address lines have been expanded to 64 bits, and the doubled bus bandwidth can provide forward and backward bidirectional compatibility for 32-bit and 64-bit PCI peripherals. The forward and backward compatible 66MHz specification is also defined, which doubles the bandwidth capability defined by 33MHz.
The PCI peripheral bus also provides a benefit to the user of a PCI-based system in that the configuration registers are defined by the PCI components and add-in cards. Systems with built-in auto-configuration software provide the user with a truly easy-to-use system that automatically configures the PCI add-in cards at power-up.
3.4 PCI Peripheral Bus Overview
The block diagram of Figure 2 shows a typical PCI local bus system architecture. This example is not intended to imply any particular architectural limitations. In this example, the processor/cache/memory subsystem is connected to the PCI bus via a PC1 bridge. This bridge provides a low-latency path that enables the processor to directly access any PCI device mapped in memory or I/O address space. It also provides a high-bandwidth path that allows PCI masters to directly access raw memory. The bridge can optionally include various functions such as data buffering/hysteresis and PCI central functions (e.g., arbitration).
Processor
Bridge/Memory
Controller
PCI Local Bus
Expansion Bus
.Audio
Basic IOwwW.bzxz.Net
ISA/EISA-MicroChannel
Figure 2 PCI System Block Diagram
TTTKAONr KAca
Tip: This standard content only shows part of the intercepted content of the complete standard. If you need the complete standard, please go to the top to download the complete standard document for free.