SJ 20758-1999 Specification for semiconductor integrated circuit CMOS gate array devices
Some standard content:
Military Standard of the Electronic Industry of the People's Republic of China FL5962
SJ20758—1999
Semiconductor integrated circuits
CMOS gate array device specification
Semiconductor integrated circuitsSpecification for COMS gate array devices1999-11-10 Issued
1999-12-01 Implementation
Approved by the Ministry of Information Industry of the People's Republic of China 1 Scope
1.1 Subject matter
1.2 Scope of application.
1.3 Classification
Absolute maximum ratings
1.5 Recommended operating conditions
2 Referenced documents
Detailed requirements
User design specification requirements
Package form
Design, structure and dimensions
Lead material and plating
Electrical characteristics
Also test requirements
Additional production line certification requirements
Functional delay simulation
Layout check
Power line simulation Proposed (when applicable)
Modify the procedures for qualified software creation
4 Quality Assurance Provisions
Sampling and Inspection
Identification Inspection
Quality Consistency Inspection
Inspection Methods
5 Delivery Preparation
Packing Requirements
Notes
6.1 Ordering Information
Abbreviations, Symbols and Definitions
Substitution
6.4 Operation
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1 Scope
People's Republic of China Electronic Industry Military Standard Semiconductor Integrated Circuit
CMOS Gate Array Device Specification
Semiconductor integrated circuitsSpecificationfor CMosgatearraydevices1.1Subject content
SJ 20758—1999
This specification specifies the detailed requirements for semiconductor integrated circuit CMOS gate array devices (hereinafter referred to as devices). 1.2Scope of application
This specification applies to the development, production and procurement of devices. 1.3Classification
The devices given in this specification are classified according to device size, device grade and packaging form. 1.3.1Device number
The device number should be in accordance with the provisions of 3.6.2 in GJB597A "General Specification for Semiconductor Integrated Circuits". 1.3.1.1 Device classification
Device classification
Released by the Ministry of Information Industry of the People's Republic of China on November 10, 1999Device scale
≤1000 gate array
≤2 000 gate array
≤3 000 gate array
≤4 000 gate array
S5 000 gate array
≤6 000 gate array
≤7 000 gate array
≤8 000 gate array
9 000 gate array
≤10 000 gate array
≤ 000 gate array
≤12000 gate array
≤15000 gate array
1999-12-01implemented
Device classification
1.3.1.2 Device grade
SJ 20758--1999
Device scale
≤25 000 gate array
≤35000 gate array
≤45000 gate array
≤55000 gate array
The device grade should be B and B1 grade specified in 3.4 of GJB597A. 1.3.1.3 Package form
The package form shall comply with the provisions of GB7092 "Outline Dimensions of Semiconductor Integrated Circuits". The package is as follows:
Note: 1) The number in the G package is the effective number of pins, 1.4 Absolute maximum ratings
Absolute human ratings are as follows;
Power supply voltage
Input and output voltage
Storage temperature
Soldering resistance (10s)
1.5 Recommended operating conditions
Recommended operating conditions are as follows:
Power supply voltage
Input voltage
Case operating temperature range
2 Reference documents
Appearance code
C44P3, C52P3
G68P2, G81P2, G120P2, G144P2, G208P2 Numerical value
GB3431.1-82 Semiconductor integrated circuit text symbols Electrical parameter text symbols GB3431.2-86 Semiconductor integrated circuit text symbols Terminal function symbols GB3439-82 Basic principles of semiconductor integrated circuit TTL circuit test methods GB3834-83 Basic principles of semiconductor integrated circuit CMOS circuit test methods - 2 -
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SJ 20758---1999
GB/T7092-93 Semiconductor integrated circuit dimensions GB/T15650-1995 Semiconductor integrated circuit series and varieties CMOS gate array circuit series varieties GJB548A-96 Microelectronic device test methods and procedures GJB597A-96 Semiconductor integrated circuit general specification GJB1208-91 Certification requirements for microcircuits
3 Requirements
3.1 Detailed requirements
All requirements should be in accordance with GJB 597A and the provisions of this specification. 3.2 Ordering Party Design Specification Requirements
The following items must be provided by the ordering party to the contractor as part of the specification. 3.2.1 Pin arrangement and purpose.
3.2.2 Package type Select from the package types provided by the contractor (see 1.3.1.3). 3.2.3 Functional block diagram.
3.2.4 Functional description, symbols and definitions.
3.2.5 Logic diagram.
3.2.6 Pin function description.
3.2.7 Circuit diagram
The circuit diagram shall comply with the provisions of GB/T15650. 3.2.8 Test vectors
The test vectors must detect at least 15% of all detectable fixed "0" state faults and fixed "1" state faults.
3.2.9 Device electrical characteristics
Device electrical characteristics shall include DC parameters (minimum requirements are shown in Table 1 of this specification), AC parameters and AC critical paths: these can be selected from the contractor's data sheet. The electrical characteristics apply to the recommended case T. operating temperature range. 3.2.10 Timing diagram
The timing diagram shall show the strict relationship between all input and output signals. The timing diagram consists of one or more diagrams that are used to show the strict relationship between two or more signals. The timing requirements for parameters such as setup time and hold time shall also be shown.
3.2.11 Burn-in circuit
The burn-in circuit is shown in Figure 1.
3.2.12 Maximum power consumption
The design shall meet the maximum power consumption requirements.
3.3 Package form
The package form shall comply with the provisions of 1.3.1.3 of this specification. 3.4 Design, Structure and Dimensions
The design, structure and dimensions shall comply with the provisions of GJB597A and this specification. 3.4.1 Die Attach Materials
Silver-containing glass (silver paste) die attach materials are permitted. 3.5 Lead Materials and Plating
SJ 20758-1999
Lead materials and plating shall comply with the provisions of 3.5.6 of GJB597A. 3.6 Electrical Characteristics
The contractor shall submit a data sheet to the appraisal agency, detailing the series or variety of gate arrays to be appraised. This data sheet shall include all DC parameters, functions and AC parameters, as well as any other data relevant to the contractor and required by the designer. All of the contractor's devices must meet the parameter limits in Table 1. All electrical characteristics apply to the recommended case operating temperature range. [The electrical characteristics of the contractor's standard evaluation circuit (SEC) (see 4.3.2.2) shall comply with the provisions of the ordering party's design specifications. ］
3.7 Electrical test requirements
The electrical test requirements for each grade of devices shall be the relevant groups specified in Table 2 of this specification. The electrical test for each group shall be specified in the ordering party's design specifications and in the SEC specifications of the contractor. The electrical test requirements shall at least meet the requirements of Figure 2 and Table 3 of this specification.
3.8 Marking
The marking shall be in accordance with the provisions of 3.6 of GJB597A: The number of the ordering party's design specification shall be added to the marking by the contractor. 3.8.1 Total radiation dose marking
The total radiation dose marking shall be in accordance with the provisions of 3.6.2.4 of GJB597A. 3.9 Additional production line certification requirements
In addition to the requirements of GJB1208, they shall also comply with the requirements of A1.1 in Appendix A of Method 5010A in GIB548A. 3.10 Functional delay simulation
shall comply with the requirements of A1.2 in Appendix A of Method 5010A in GJB548A. 3.11 Layout verification
shall comply with the requirements of A1.3 in Appendix A of Method 5010A in GJB548A. 3.12 Power line simulation (when applicable)
Shall comply with the requirements of A1.4 in Appendix A of Method 5010A of GJB548A. 3.13 Procedure for modifying qualified software packages The contractor shall submit a verification procedure to the certification body for accepting modifications and revisions of qualified software packages. For the process of accepting/rejecting modifications and revisions of internal or commercial software packages, this procedure shall briefly describe its methods and provide test instructions for the use of the process. This requirement only applies to the software packages used by the contractor in the gate array design process.
Table 1 Electrical characteristics
Input positive clamp voltage
Input negative clamp voltage
Output high level voltage
Unless otherwise specified, -55℃≤T≤125℃Vrp=5 V+10%)
Vpp is grounded, and the input terminal under test Ik=I mA. All input terminals are measured
Vss is grounded, and the input terminal under test ik=-1 mA.
Measure all input terminals
TTL connection: loH -2 mA
CMOS connection: JoH ≤-1 μA
Limit value
Contractor data
Contractor data
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Output low voltage
Input high voltage
Input low voltage
Input high current
Input low current
Output high-state high current
Output off-state low current
Quiet supply current
Input capacitance
Output capacitance
Intermediate (before aging) electrical test
Intermediate (after aging) electrical test
Final electrical test
A test electrical test
B end electrical test
C end electrical test
D end electrical test
SJ 20758--1999
Continued Table 1
(If not otherwise specified, -55°℃≤T≤125°℃Vpp*=5 V±10%)
TTL interface: IoL =2.4 mA
CMOS interface: uL IμA
TTL interface
CMOS interface
TTL interface
CMOS interface
Vo-Yss
Only applicable to those without pull-up or pull-down
Only applicable to those without pull-up or pull-down
F1 MH., T. -25 °℃
f-1 MHz, Tc-25°C
Table 2 Electrical test requirements
Grouping (see Table 3)
Limit value
As per design requirements
Change limit
Al, A2, A3, A7, A8a, A8b, A9, At0, A11Al, A2+ A3+ A4, A7, A8a, A8b, A9, A10, A11Al
Note: 1) This grouping requires PDA calculation (see 4.2 of this specification). 4 2)
2) Changes in aging and life test requirements (4) Measurement is only applicable to A2 grouping. The change limit shall be in accordance with 4.5.2 of this specification.
Reference Standards
GB3834
GE3439
GB3439
SJ 20758-1999
Table 3 Electrical Test
(Unless otherwise specified, GND=0V, Te=25°C)Vep grounded, input terminal under test Iik =1 mA. Test all input terminals
Vs grounded, input terminal under test Iik=1 mA. Test all input terminals
V=4.5 V, test all applicable output terminals.
Ypp=4.5 V, all applicable output terminals.
TTL: IoH *-2 mA
CMOS: JoH ≤-1 μA
TTL: ToL -2.4 mA
CMOS: JOL SIμA
Vpp-5.5 V, V'l=5.5 V,
Measure all input terminals.
YDD-=5.5 V, V'=0 V,
Measure all input terminals.
Von=5.5 V, Yo-Ved*
Measure all output terminals.
Vpp=5.5 V, Vo-0 V,
Measure all output terminals:
Applies only to devices without pull-up or
pull-down
Applies only to devices without pull-up or
pull-down
Vpp-5.5 V, measure Vpp terminal.
Tc=125°C, all parameters, conditions and specification values are grouped with A1. 7. --55°C. All parameters, conditions and specification values are grouped with A1. G
F-1MHz, measure the capacitance of all input terminals to GND. f1 MHz, measure the capacitance of all output terminals to GND. Ypp=4.5V: According to the design performance: Meet the user design specification requirements. See Figure 2. T=125\C, others are grouped with A7.
Tc --55 °C, other same as A7 group
Yop*4.5V. According to the design performance: meet the user design specification requirements. See Figure 2. Tc-125°C, other same as A9 group,
Tc--55\C, other same as A9 group.
Note: 1) If one end of the test is specially designed, it must be stated in the user design specification. Limit value
Maximum
According to the data of the manufacturer
According to the data of the manufacturer
According to the design requirements
2) The test loss for realizing the function and switching characteristic detection is specially designed and must be included in the user design specification. The measurement system must meet the requirements of 3.2.8 of this specification. The limit value is specified in the user design specification. 4 Quality Assurance Provisions
4.1 Sampling and Inspection
Except as otherwise specified in this specification, the sampling and inspection procedures shall be in accordance with the provisions of GJB597A and GJB548A Method 5005A-6-
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4.2 Screening
SJ20758—1999
Before the identification inspection and quality conformity inspection, all devices shall be inspected and tested according to GJB548A Screening is carried out according to the provisions of Method 5004A and Table 4 of this specification.
Table 4 Screening Procedure
If there is no other provision, the method used in the table refers to the test method of GJB548A. Screening Item Date
Internal Visual Inspection (Before Packaging)
Stability Baking
(End-point Electrical Test is Not Required)
Temperature Cycling
Constant Acceleration
Intermediate (Before Aging) Electrical Test
Intermediate (After Aging) Electrical Test
Allowed Defective Rate (PDA)
and its calculation
Final Electrical Test
Rough Leakage Detection
External Visual Inspection
Test Sample Extraction for Qualification and Quality Consistency Inspection
4.3 Qualification Inspection
4. 3.1 Verification test
Conditions and requirements
Test condition B
Test condition C
(150°C, 24 h)
Test condition C
Test condition DY1 Direction
Group A2 of this specification
Test miscellaneous items A
125°C, 160 h
Test condition D
125°C,160 h
Group A2 of this specification
and limit of Table 104
10%. When the defective rate
does not exceed 20%, it can be resubmitted for aging, but only once is allowed.
Group A1, A2, A3 of this specification.
A4, A7 A8a, A8b.
A9, A10. A11
Test conditions: A1 or A2
Test conditions: CI or C2
Visual inspection after the test, broken leads, broken shells, and falling covers are considered failures.
When calculating PDA using 4 limit values, it is required to record the Iops value.
Use the circuit shown in Figure 1 of this specification. You can choose either static or dynamic aging. The PDA is calculated by dividing the number of aging failures (devices exceeding the 42-group extreme limit or exceeding the 4-group ging value) by the number of devices submitted for aging. If it is not greater than the specified PDA, the batch should be accepted. After this screening, if the lead plating is changed or reworked, the A1 group test should be carried out again. The qualification inspection should be in accordance with the provisions of 4.4 of GJB597A. The inspection should comply with the provisions of GJB548A Method 5005A-7 - SJ 20758-1999 and the A, B, C, D and E group inspections of this specification (see 4.4.1 to 4.4.5 of this specification). In addition, the following 5 qualification stages should be completed with a certain qualification media. 4.3.2 Qualification Phase and Media
Qualification Phase
Process Monitoring and Stability
Process Reliability
Macrocell Design and Simulation
CAD Routing and Post-routing Simulation
Design Check Software Verification
Qualification Media
I. Process Monitoring Pattern (PM)
Standard Evaluation Circuit (SEC)
Macrocell Test Chip Pattern
Test Pattern Standard for Gate Array
Test Conditions of the Contractor
Qualification of macrocell design and simulation, as well as CAD routing and post-routing simulation shall be based on the contractor’s design, layout and routing capabilities, and the measured performance characteristics of the contractor’s devices (such as transmission delay, rise and fall time, drive characteristics, trigger level, etc.) shall be within the simulated performance characteristics limit values (see 4.3.2.4). YD
1op/2~YpD
Note: ①For static aging, all input terminals are connected to Ppp through resistors, and the output is open circuit or connected to Vpp through resistors. 12~Vpp resistor R=6802~47k2, the actual resistance value should reflect the most stringent load conditions. If the output is open circuit, the output terminal resistor can be selected.
②For dynamic aging, all input terminals are connected to the clock pulse (CP) through resistors, and the output terminal is connected to Vop/2+0.5V through resistors. Input terminal resistor R=680247k2, output terminal resistor R=1k2±5% input signal requirements, square wave: duty cycle is 50%±15%: frequency fcp=100kHzt50% amplitude: Vi-4.5 V~Ypm Vu=0±0.5 V. Conversion time ≤0.5 μs. ? Vpn=5.0 V±0.5 V.
④}-input terminal; 0 output terminal: N (M)-the input (output) terminal with the largest number. ③In the case of multiple power supply terminals or multiple block terminals, all power supplies or ground terminals should be connected to the corresponding level. ③The terminal symbol is determined by the user.
Figure 1 Static, dynamic aging and steady-state life test circuit diagram 8-
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Blue state output test circuit diagram
c. Waveform diagram
SJ20758--1999
Standard output test circuit diagram
Test point
Note: ①C=50pF±10%, including probe and fixture capacitance. Device
-test point
②Input pulse characteristics: 4≤6ns: F1MHz; duty cycle: 50%. ③ All unused input terminals are connected to Ypp or GND. @ IThli- ttHL2* tThLi tTlh2- Itlhi= ITlho③ When the escape function test and all AC tests (except the output enable test), S1 is closed. For the ipzH test, when S2 is connected, S1 and S3 are closed. For the tpzL test, when S3 is connected, SI and S2 are closed. ① For the three-state output, R,=1kQ+10%. For the non-three-state output, Rz is determined by lon under the condition of VoH=2.4V. ③R, determined by loL (minimum value) at Yn-0.05V minus the current through R to ground, Figure 2 Switch test circuit and waveform diagram
4.3.2.1T. Process control and stability
SJ 20758—1999
The process control and stability of DC parameters must be demonstrated by the contractor and the process monitoring diagram (PM). For the test of DC process parameters (the contractor can choose whether to include AC parameters), PM (or specially inserted or placed in the dicing groove) can be designed in wafer form or packaged device form. The PM design should be submitted to the appraisal organization for approval before appraisal and should include at least the following structures: a. N-channel device (minimum structure)
b. P-channel device (minimum structure)
N-channel device (large device)
P-channel device (large device)
Sheet resistance test structure
Metal step distribution structure
Field reading device
h. Intermetallic oxide integrity structure
Connection chain (length should be sufficient to represent contact resistance) (1) Metal to polycrystalline (when applicable)
(2) Channel resistance of metal 1 to metal 2 (when applicable). (3) Inverter chain (for AC testing: determined by the contractor). (4) Metal to diffusion layer (when applicable). For appraisal, PMs from at least 3 different batches (at least 4 PMs per wafer) should be tested to ensure the establishment of valid statistical data, which can be used as a basis for judging whether the contractor's process is stable and controlled. The most recent batch historical data may be used to meet this requirement (at the option of the contractor). 4.3.2.2 Process Reliability
The SEC (Standard Evaluation Circuit) may be used to evaluate process reliability. The SEC design shall include the basic information described in 3.2.1 to 3.2.1C and shall be submitted to the certification authority for approval before using the contractor's ordering design specification. Its manufacturing process is the same as that used to produce any dedicated gate array device to this specification. The SEC shall be designed to evaluate the reliability of the underlying design (diffusion, etc.) and the worst-case conditions of the design rules. The design shall utilize a macrocell library and form oscillating loops and various test structures that can detect metal-to-metal shorts or opens, high through-hole resistance and dielectric pinholes during reliability life testing. The SEC shall be implemented on the largest scale device (i.e., the device with the largest number of gates in the device category, and if applicable, the gate array package should have the largest number of pins). The qualification of the device varieties with the largest number of pins and the smaller number of gates or the device varieties with the smaller number of pins and the smaller number of gates in the gate array series of the contractor is carried out by extension (see 4.3.3). For the following (4.4.1, 4.4.2, 4.4.3, 4.4.4) electrical tests, the SEC is also the main qualification medium. For the SEC request of the contractor, the test limits are specified in the design specification of the ordering party (for the minimum requirements of DC parameters, see Table 1 of this specification). The electrical tests of each group are carried out as specified in Table 3. When the SEC is subjected to life testing (see 4.4.3), static bias aging should be applied. 4.3.2.3 The qualification of macrocell design and simulation shall comply with the requirements of A1.5 of Appendix A of Method 5010A in GJB548A. 4.3.2.4 CAD layout and post-layout simulation
shall comply with the requirements of A1.6 of Appendix A of Method 5010A in GJB548A. 4.3.2.5 Verification of design check software
TTTKAONrKAca-A11 Group
Test conditions: A1 or A2
Test conditions: CI or C2
After the test, visual inspection is carried out. Failures are caused by broken leads, cracked shells, and detached covers. When calculating PDA using the 4 limit values, it is required to record the Iops value. The circuit shown in Figure 1 of this specification is used. Either static or dynamic aging can be selected. The PDA is obtained by dividing the number of aging failures (devices exceeding the 42 group extreme
limit or exceeding the 4 extreme values) by the number of devices submitted for aging. If it is not greater than the specified PDA, the batch should be accepted.
After this screening, if the lead plating is changed or reworked, the A1 group test should be carried out again. The identification test should be in accordance with the provisions of 4.4 in GJB597A. The inspection should comply with the provisions of GJB548A Method 5005A-7 -
SJ 20758—1999
and the A, B, C, D and E group inspections of this specification (see 4.4.1 to 4.4.5 of this specification). In addition, the following 5 identification stages should be completed with the specified identification media. 4.3.2 Qualification Phase and Media
Qualification Phase
Process Monitoring and Stability
Process Reliability
Macrocell Design and Simulation
CAD Routing and Post-routing Simulation
Design Check Software Verification
Qualification Media
I. Process Monitoring Pattern (PM)
Standard Evaluation Circuit (SEC)
Macrocell Test Chip Pattern
Test Pattern Standard for Gate Array
Test Conditions of the Contractor
Qualification of macrocell design and simulation, as well as CAD routing and post-routing simulation shall be based on the contractor’s design, layout and routing capabilities, and the measured performance characteristics of the contractor’s devices (such as transmission delay, rise and fall time, drive characteristics, trigger level, etc.) shall be within the simulated performance characteristics limit values (see 4.3.2.4). YD
1op/2~YpD
Note: ①For static aging, all input terminals are connected to Ppp through resistors, and the output is open circuit or connected to Vpp through resistors. 12~Vpp resistor R=6802~47k2, the actual resistance value should reflect the most stringent load conditions. If the output is open circuit, the output terminal resistor can be selected.
②For dynamic aging, all input terminals are connected to the clock pulse (CP) through resistors, and the output terminal is connected to Vop/2+0.5V through resistors. Input terminal resistor R=680247k2, output terminal resistor R=1k2±5% input signal requirements, square wave: duty cycle is 50%±15%: frequency fcp=100kHzt50% amplitude: Vi-4.5 V~Ypm Vu=0±0.5 V. Conversion time ≤0.5 μs. ? Vpn=5.0 V±0.5 V.
④}-input terminal; 0 output terminal: N (M)-the input (output) terminal with the largest number. ③In the case of multiple power supply terminals or multiple block terminals, all power supplies or ground terminals should be connected to the corresponding level. ③The terminal symbol is determined by the user.
Figure 1 Static, dynamic aging and steady-state life test circuit diagram 8-
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Blue state output test circuit diagram
c. Waveform diagram
SJ20758--1999
Standard output test circuit diagram
Test point
Note: ①C=50pF±10%, including probe and fixture capacitance. Device
-test point
②Input pulse characteristics: 4≤6ns: F1MHz; duty cycle: 50%. ③ All unused input terminals are connected to Ypp or GND. @ IThli- ttHL2* tThLi tTlh2- Itlhi= ITlho③ When the escape function test and all AC tests (except the output enable test), S1 is closed. For the ipzH test, when S2 is connected, S1 and S3 are closed. For the tpzL test, when S3 is connected, SI and S2 are closed. ① For the three-state output, R,=1kQ+10%. For the non-three-state output, Rz is determined by lon under the condition of VoH=2.4V. ③R, determined by loL (minimum value) at Yn-0.05V minus the current through R to ground, Figure 2 Switch test circuit and waveform diagram
4.3.2.1T. Process control and stability
SJ 20758—1999
The process control and stability of DC parameters must be demonstrated by the contractor and the process monitoring diagram (PM). For the test of DC process parameters (the contractor can choose whether to include AC parameters), PM (or specially inserted or placed in the dicing groove) can be designed in wafer form or packaged device form. The PM design should be submitted to the appraisal organization for approval before appraisal and should include at least the following structures: a. N-channel device (minimum structure)
b. P-channel device (minimum structure)
N-channel device (large device)
P-channel device (large device)
Sheet resistance test structure
Metal step distribution structure
Field reading device
h. Intermetallic oxide integrity structure
Connection chain (length should be sufficient to represent contact resistance) (1) Metal to polycrystalline (when applicable)
(2) Channel resistance of metal 1 to metal 2 (when applicable). (3) Inverter chain (for AC testing: determined by the contractor). (4) Metal to diffusion layer (when applicable). For appraisal, PMs from at least 3 different batches (at least 4 PMs per wafer) should be tested to ensure the establishment of valid statistical data, which can be used as a basis for judging whether the contractor's process is stable and controlled. The most recent batch historical data may be used to meet this requirement (at the option of the contractor). 4.3.2.2 Process Reliability
The SEC (Standard Evaluation Circuit) may be used to evaluate process reliability. The SEC design shall include the basic information described in 3.2.1 to 3.2.1C and shall be submitted to the certification authority for approval before using the contractor's ordering design specification. Its manufacturing process is the same as that used to produce any dedicated gate array device to this specification. The SEC shall be designed to evaluate the reliability of the underlying design (diffusion, etc.) and the worst-case conditions of the design rules. The design shall utilize a macrocell library and form oscillating loops and various test structures that can detect metal-to-metal shorts or opens, high through-hole resistance and dielectric pinholes during reliability life testing. The SEC shall be implemented on the largest scale device (i.e., the device with the largest number of gates in the device category, and if applicable, the gate array package should have the largest number of pins). The qualification of the device varieties with the largest number of pins and the smaller number of gates or the device varieties with the smaller number of pins and the smaller number of gates in the gate array series of the contractor is carried out by extension (see 4.3.3). For the following (4.4.1, 4.4.2, 4.4.3, 4.4.4) electrical tests, the SEC is also the main qualification medium. For the SEC request of the contractor, the test limits are specified in the design specification of the ordering party (for the minimum requirements of DC parameters, see Table 1 of this specification). The electrical tests of each group are carried out as specified in Table 3. When the SEC is subjected to life testing (see 4.4.3), static bias aging should be applied. 4.3.2.3 The qualification of macrocell design and simulation shall comply with the requirements of A1.5 of Appendix A of Method 5010A in GJB548A. 4.3.2.4 CAD layout and post-layout simulation
shall comply with the requirements of A1.6 of Appendix A of Method 5010A in GJB548A. 4.3.2.5 Verification of design check software
TTTKAONrKAca-A11 Group
Test conditions: A1 or A2
Test conditions: CI or C2
After the test, visual inspection is carried out. Failures are caused by broken leads, cracked shells, and detached covers. When calculating PDA using the 4 limit values, it is required to record the Iops value. The circuit shown in Figure 1 of this specification is used. Either static or dynamic aging can be selected. The PDA is obtained by dividing the number of aging failures (devices exceeding the 42 group extreme
limit or exceeding the 4 extreme values) by the number of devices submitted for aging. If it is not greater than the specified PDA, the batch should be accepted.
After this screening, if the lead plating is changed or reworked, the A1 group test should be carried out again. The identification test should be in accordance with the provisions of 4.4 in GJB597A. The inspection should comply with the provisions of GJB548A Method 5005A-7 -
SJ 20758—1999
and the A, B, C, D and E group inspections of this specification (see 4.4.1 to 4.4.5 of this specification). In addition, the following 5 identification stages should be completed with the specified identification media. 4.3.2 Qualification Phase and Media
Qualification Phase
Process Monitoring and Stability
Process Reliability
Macrocell Design and Simulation
CAD Routing and Post-routing Simulation
Design Check Software Verification
Qualification Media
I. Process Monitoring Pattern (PM)
Standard Evaluation Circuit (SEC)
Macrocell Test Chip Pattern
Test Pattern Standard for Gate Array
Test Conditions of the Contractor
Qualification of macrocell design and simulation, as well as CAD routing and post-routing simulation shall be based on the contractor’s design, layout and routing capabilities, and the measured performance characteristics of the contractor’s devices (such as transmission delay, rise and fall time, drive characteristics, trigger level, etc.) shall be within the simulated performance characteristics limit values (see 4.3.2.4). YD
1op/2~YpD
Note: ①For static aging, all input terminals are connected to Ppp through resistors, and the output is open circuit or connected to Vpp through resistors. 12~Vpp resistor R=6802~47k2, the actual resistance value should reflect the most stringent load conditions. If the output is open circuit, the output terminal resistor can be selected.
②For dynamic aging, all input terminals are connected to the clock pulse (CP) through resistors, and the output terminal is connected to Vop/2+0.5V through resistors. Input terminal resistor R=680247k2, output terminal resistor R=1k2±5% input signal requirements, square wave: duty cycle is 50%±15%: frequency fcp=100kHzt50% amplitude: Vi-4.5 V~Ypm Vu=0±0.5 V. Conversion time ≤0.5 μs. ? Vpn=5.0 V±0.5 V.
④}-input terminal; 0 output terminal: N (M)-the input (output) terminal with the largest number. ③In the case of multiple power supply terminals or multiple block terminals, all power supplies or ground terminals should be connected to the corresponding level. ③The terminal symbol is determined by the user.
Figure 1 Static, dynamic aging and steady-state life test circuit diagram 8-
TTTKAONrKAca
Blue state output test circuit diagram
c. Waveform diagram
SJ20758--1999
Standard output test circuit diagram
Test point
Note: ①C=50pF±10%, including probe and fixture capacitance. Device
-test point
②Input pulse characteristics: 4≤6ns: F1MHz; duty cycle: 50%. ③ All unused input terminals are connected to Ypp or GND. @ IThli- ttHL2* tThLi tTlh2- Itlhi= ITlho③ When the escape function test and all AC tests (except the output enable test), S1 is closed. For the ipzH test, when S2 is connected, S1 and S3 are closed. For the tpzL test, when S3 is connected, SI and S2 are closed. ① For the three-state output, R,=1kQ+10%. For the non-three-state output, Rz is determined by lon under the condition of VoH=2.4V. ③R, determined by loL (minimum value) at Yn-0.05V minus the current through R to ground, Figure 2 Switch test circuit and waveform diagram
4.3.2.1T. Process control and stability
SJ 20758—1999wwW.bzxz.Net
The process control and stability of DC parameters must be demonstrated by the contractor and the process monitoring diagram (PM). For the test of DC process parameters (the contractor can choose whether to include AC parameters), PM (or specially inserted or placed in the dicing groove) can be designed in wafer form or packaged device form. The PM design should be submitted to the appraisal organization for approval before appraisal and should include at least the following structures: a. N-channel device (minimum structure)
b. P-channel device (minimum structure)
N-channel device (large device)
P-channel device (large device)
Sheet resistance test structure
Metal step distribution structure
Field reading device
h. Intermetallic oxide integrity structure
Connection chain (length should be sufficient to represent contact resistance) (1) Metal to polycrystalline (when applicable)
(2) Channel resistance of metal 1 to metal 2 (when applicable). (3) Inverter chain (for AC testing: determined by the contractor). (4) Metal to diffusion layer (when applicable). For appraisal, PMs from at least 3 different batches (at least 4 PMs per wafer) should be tested to ensure the establishment of valid statistical data, which can be used as a basis for judging whether the contractor's process is stable and controlled. The most recent batch historical data may be used to meet this requirement (at the option of the contractor). 4.3.2.2 Process Reliability
The SEC (Standard Evaluation Circuit) may be used to evaluate process reliability. The SEC design shall include the basic information described in 3.2.1 to 3.2.1C and shall be submitted to the certification authority for approval before using the contractor's ordering design specification. Its manufacturing process is the same as that used to produce any dedicated gate array device to this specification. The SEC shall be designed to evaluate the reliability of the underlying design (diffusion, etc.) and the worst-case conditions of the design rules. The design shall utilize a macrocell library and form oscillating loops and various test structures that can detect metal-to-metal shorts or opens, high through-hole resistance and dielectric pinholes during reliability life testing. The SEC shall be implemented on the largest scale device (i.e., the device with the largest number of gates in the device category, and if applicable, the gate array package should have the largest number of pins). The qualification of the device varieties with the largest number of pins and the smaller number of gates or the device varieties with the smaller number of pins and the smaller number of gates in the gate array series of the contractor is carried out by extension (see 4.3.3). For the following (4.4.1, 4.4.2, 4.4.3, 4.4.4) electrical tests, the SEC is also the main qualification medium. For the SEC request of the contractor, the test limits are specified in the design specification of the ordering party (for the minimum requirements of DC parameters, see Table 1 of this specification). The electrical tests of each group are carried out as specified in Table 3. When the SEC is subjected to life testing (see 4.4.3), static bias aging should be applied. 4.3.2.3 The qualification of macrocell design and simulation shall comply with the requirements of A1.5 of Appendix A of Method 5010A in GJB548A. 4.3.2.4 CAD layout and post-layout simulation
shall comply with the requirements of A1.6 of Appendix A of Method 5010A in GJB548A. 4.3.2.5 Verification of design check software
TTTKAONrKAca-2 Qualification Phase and Media
Qualification Phase
Process Monitoring and Stability
Process Reliability
Macrocell Design and Simulation
CAD Routing and Post-routing Simulation
Design Check Software Verification
Qualification Media
I. Process Monitoring Pattern (PM)
Standard Evaluation Circuit (SEC)
Macrocell Test Chip Pattern
Test Pattern Standard for Gate Array
Test Conditions of the Contractor
Qualification of macrocell design and simulation, as well as CAD routing and post-routing simulation shall be based on the contractor’s design, layout and routing capabilities, and the measured performance characteristics of the contractor’s devices (such as transmission delay, rise and fall time, drive characteristics, trigger level, etc.) shall be within the simulated performance characteristics limit values (see 4.3.2.4). YD
1op/2~YpD
Note: ①For static aging, all input terminals are connected to Ppp through resistors, and the output is open circuit or connected to Vpp through resistors. 12~Vpp resistor R=6802~47k2, the actual resistance value should reflect the most stringent load conditions. If the output is open circuit, the output terminal resistor can be selected.
②For dynamic aging, all input terminals are connected to the clock pulse (CP) through resistors, and the output terminal is connected to Vop/2+0.5V through resistors. Input terminal resistor R=680247k2, output terminal resistor R=1k2±5% input signal requirements, square wave: duty cycle is 50%±15%: frequency fcp=100kHzt50% amplitude: Vi-4.5 V~Ypm Vu=0±0.5 V. Conversion time ≤0.5 μs. ? Vpn=5.0 V±0.5 V.
④}-input terminal; 0 output terminal: N (M)-the input (output) terminal with the largest number. ③In the case of multiple power supply terminals or multiple block terminals, all power supplies or ground terminals should be connected to the corresponding level. ③The terminal symbol is determined by the user.
Figure 1 Static, dynamic aging and steady-state life test circuit diagram 8-
TTTKAONrKAca
Blue state output test circuit diagram
c. Waveform diagram
SJ20758--1999
Standard output test circuit diagram
Test point
Note: ①C=50pF±10%, including probe and fixture capacitance. Device
-test point
②Input pulse characteristics: 4≤6ns: F1MHz; duty cycle: 50%. ③ All unused input terminals are connected to Ypp or GND. @ IThli- ttHL2* tThLi tTlh2- Itlhi= ITlho③ When the escape function test and all AC tests (except the output enable test), S1 is closed. For the ipzH test, when S2 is connected, S1 and S3 are closed. For the tpzL test, when S3 is connected, SI and S2 are closed. ① For the three-state output, R,=1kQ+10%. For the non-three-state output, Rz is determined by lon under the condition of VoH=2.4V. ③R, determined by loL (minimum value) at Yn-0.05V minus the current through R to ground, Figure 2 Switch test circuit and waveform diagram
4.3.2.1T. Process control and stability
SJ 20758—1999
The process control and stability of DC parameters must be demonstrated by the contractor and the process monitoring diagram (PM). For the test of DC process parameters (the contractor can choose whether to include AC parameters), PM (or specially inserted or placed in the dicing groove) can be designed in wafer form or packaged device form. The PM design should be submitted to the appraisal organization for approval before appraisal and should include at least the following structures: a. N-channel device (minimum structure)
b. P-channel device (minimum structure)
N-channel device (large device)
P-channel device (large device)
Sheet resistance test structure
Metal step distribution structure
Field reading device
h. Intermetallic oxide integrity structure
Connection chain (length should be sufficient to represent contact resistance) (1) Metal to polycrystalline (when applicable)
(2) Channel resistance of metal 1 to metal 2 (when applicable). (3) Inverter chain (for AC testing: determined by the contractor). (4) Metal to diffusion layer (when applicable). For appraisal, PMs from at least 3 different batches (at least 4 PMs per wafer) should be tested to ensure the establishment of valid statistical data, which can be used as a basis for judging whether the contractor's process is stable and controlled. The most recent batch historical data may be used to meet this requirement (at the option of the contractor). 4.3.2.2 Process Reliability
The SEC (Standard Evaluation Circuit) may be used to evaluate process reliability. The SEC design shall include the basic information described in 3.2.1 to 3.2.1C and shall be submitted to the certification authority for approval before using the contractor's ordering design specification. Its manufacturing process is the same as that used to produce any dedicated gate array device to this specification. The SEC shall be designed to evaluate the reliability of the underlying design (diffusion, etc.) and the worst-case conditions of the design rules. The design shall utilize a macrocell library and form oscillating loops and various test structures that can detect metal-to-metal shorts or opens, high through-hole resistance and dielectric pinholes during reliability life testing. The SEC shall be implemented on the largest scale device (i.e., the device with the largest number of gates in the device category, and if applicable, the gate array package should have the largest number of pins). The qualification of the device varieties with the largest number of pins and the smaller number of gates or the device varieties with the smaller number of pins and the smaller number of gates in the gate array series of the contractor is carried out by extension (see 4.3.3). For the following (4.4.1, 4.4.2, 4.4.3, 4.4.4) electrical tests, the SEC is also the main qualification medium. For the SEC request of the contractor, the test limits are specified in the design specification of the ordering party (for the minimum requirements of DC parameters, see Table 1 of this specification). The electrical tests of each group are carried out as specified in Table 3. When the SEC is subjected to life testing (see 4.4.3), static bias aging should be applied. 4.3.2.3 The qualification of macrocell design and simulation shall comply with the requirements of A1.5 of Appendix A of Method 5010A in GJB548A. 4.3.2.4 CAD layout and post-layout simulation
shall comply with the requirements of A1.6 of Appendix A of Method 5010A in GJB548A. 4.3.2.5 Verification of design check software
TTTKAONrKAca-2 Qualification Phase and Media
Qualification Phase
Process Monitoring and Stability
Process Reliability
Macrocell Design and Simulation
CAD Routing and Post-routing Simulation
Design Check Software Verification
Qualification Media
I. Process Monitoring Pattern (PM)
Standard Evaluation Circuit (SEC)
Macrocell Test Chip Pattern
Test Pattern Standard for Gate Array
Test Conditions of the Contractor
Qualification of macrocell design and simulation, as well as CAD routing and post-routing simulation shall be based on the contractor’s design, layout and routing capabilities, and the measured performance characteristics of the contractor’s devices (such as transmission delay, rise and fall time, drive characteristics, trigger level, etc.) shall be within the simulated performance characteristics limit values (see 4.3.2.4). YD
1op/2~YpD
Note: ①For static aging, all input terminals are connected to Ppp through resistors, and the output is open circuit or connected to Vpp through resistors. 12~Vpp resistor R=6802~47k2, the actual resistance value should reflect the most stringent load conditions. If the output is open circuit, the output terminal resistor can be selected.
②For dynamic aging, all input terminals are connected to the clock pulse (CP) through resistors, and the output terminal is connected to Vop/2+0.5V through resistors. Input terminal resistor R=680247k2, output terminal resistor R=1k2±5% input signal requirements, square wave: duty cycle is 50%±15%: frequency fcp=100kHzt50% amplitude: Vi-4.5 V~Ypm Vu=0±0.5 V. Conversion time ≤0.5 μs. ? Vpn=5.0 V±0.5 V.
④}-input terminal; 0 output terminal: N (M)-the input (output) terminal with the largest number. ③In the case of multiple power supply terminals or multiple block terminals, all power supplies or ground terminals should be connected to the corresponding level. ③The terminal symbol is determined by the user.
Figure 1 Static, dynamic aging and steady-state life test circuit diagram 8-
TTTKAONrKAca
Blue state output test circuit diagram
c. Waveform diagram
SJ20758--1999
Standard output test circuit diagram
Test point
Note: ①C=50pF±10%, including probe and fixture capacitance. Device
-test point
②Input pulse characteristics: 4≤6ns: F1MHz; duty cycle: 50%. ③ All unused input terminals are connected to Ypp or GND. @ IThli- ttHL2* tThLi tTlh2- Itlhi= ITlho③ When the escape function test and all AC tests (except the output enable test), S1 is closed. For the ipzH test, when S2 is connected, S1 and S3 are closed. For the tpzL test, when S3 is connected, SI and S2 are closed. ① For the three-state output, R,=1kQ+10%. For the non-three-state output, Rz is determined by lon under the condition of VoH=2.4V. ③R, determined by loL (minimum value) at Yn-0.05V minus the current through R to ground, Figure 2 Switch test circuit and waveform diagram
4.3.2.1T. Process control and stability
SJ 20758—1999
The process control and stability of DC parameters must be demonstrated by the contractor and the process monitoring diagram (PM). For the test of DC process parameters (the contractor can choose whether to include AC parameters), PM (or specially inserted or placed in the dicing groove) can be designed in wafer form or packaged device form. The PM design should be submitted to the appraisal organization for approval before appraisal and should include at least the following structures: a. N-channel device (minimum structure)
b. P-channel device (minimum structure)
N-channel device (large device)
P-channel device (large device)
Sheet resistance test structure
Metal step distribution structure
Field reading device
h. Intermetallic oxide integrity structure
Connection chain (length should be sufficient to represent contact resistance) (1) Metal to polycrystalline (when applicable)
(2) Channel resistance of metal 1 to metal 2 (when applicable). (3) Inverter chain (for AC testing: determined by the contractor). (4) Metal to diffusion layer (when applicable). For appraisal, PMs from at least 3 different batches (at least 4 PMs per wafer) should be tested to ensure the establishment of valid statistical data, which can be used as a basis for judging whether the contractor's process is stable and controlled. The most recent batch historical data may be used to meet this requirement (at the option of the contractor). 4.3.2.2 Process Reliability
The SEC (Standard Evaluation Circuit) may be used to evaluate process reliability. The SEC design shall include the basic information described in 3.2.1 to 3.2.1C and shall be submitted to the certification authority for approval before using the contractor's ordering design specification. Its manufacturing process is the same as that used to produce any dedicated gate array device to this specification. The SEC shall be designed to evaluate the reliability of the underlying design (diffusion, etc.) and the worst-case conditions of the design rules. The design shall utilize a macrocell library and form oscillating loops and various test structures that can detect metal-to-metal shorts or opens, high through-hole resistance and dielectric pinholes during reliability life testing. The SEC shall be implemented on the largest scale device (i.e., the device with the largest number of gates in the device category, and if applicable, the gate array package should have the largest number of pins). The qualification of the device varieties with the largest number of pins and the smaller number of gates or the device varieties with the smaller number of pins and the smaller number of gates in the gate array series of the contractor is carried out by extension (see 4.3.3). For the following (4.4.1, 4.4.2, 4.4.3, 4.4.4) electrical tests, the SEC is also the main qualification medium. For the SEC request of the contractor, the test limits are specified in the design specification of the ordering party (for the minimum requirements of DC parameters, see Table 1 of this specification). The electrical tests of each group are carried out as specified in Table 3. When the SEC is subjected to life testing (see 4.4.3), static bias aging should be applied. 4.3.2.3 The qualification of macrocell design and simulation shall comply with the requirements of A1.5 of Appendix A of Method 5010A in GJB548A. 4.3.2.4 CAD layout and post-layout simulation
shall comply with the requirements of A1.6 of Appendix A of Method 5010A in GJB548A. 4.3.2.5 Verification of design check software
TTTKAONrKAca-
④}-input terminal; 0 output terminal: N (M)-the input (output) terminal with the largest number. ③In the case of multiple power supply terminals or multiple block terminals, all power supplies or ground terminals should be connected to the corresponding level. ③The terminal symbol is determined by the user.
Figure 1 Static, dynamic aging and steady-state life test circuit diagram 8-
TTTKAONrKAca
Blue state output test circuit diagram
c. Waveform diagram
SJ20758--1999
Standard output test circuit diagram
Test point
Note: ①C=50pF±10%, including probe and fixture capacitance. Device
-test point
②Input pulse characteristics: 4≤6ns: F1MHz; duty cycle: 50%. ③All unused input terminals are connected to Ypp or GND. @ IThli- ttHL2* tThLi tTlh2- Itlhi= ITlho③S1 is closed during the escape function test and all AC tests (except the output enable test). For the ipzH test, when S2 is connected, S1 and S3 are closed. For the tpzL test, when S3 is connected, SI and S2 are closed. ①For the three-state output, R,=1kQ+10%. For the non-three-state output, Rz is determined by lon under the condition of VoH=2.4V. ③R, is determined by loL (minimum value) at Yn-0.05V minus the current through R to ground, Figure 2 Switching test circuit and waveform diagram
4.3.2.1T. Process control and stability
SJ 20758—1999
The process control and stability of DC parameters must be demonstrated by the contractor and the process monitoring diagram (PM). For testing of DC process parameters (AC parameters can be included at the option of the contractor), PM (or specially inserted or placed in the scribe groove) can be designed in wafer form or packaged device form. PM design should be submitted to the certification body for approval before certification and include at least the following structures: a N-channel device (minimum structure)
b, P-channel device (minimum structure)
N-channel device (large device)
P-channel device (large device)
Sheet resistance test structure
Metal step distribution structure
Field reading value device
h. Intermetallic oxide integrity structure
Connection chain (length should be sufficient to represent contact resistance) (1) Metal to polycrystalline (when applicable)
(2) Channel resistance of metal 1 to metal 2 (when applicable). (3) Inverter chain (for AC testing: determined by the contractor). (4) Metal to diffusion layer (when applicable). For qualification, a minimum of 3 different batches of PMs (4 PMs per wafer) shall be tested to ensure that valid statistics are established and used as a basis for judging whether the contractor's process is stable and controlled. Historical data from the most recent batch may be used to meet this requirement (at the contractor's option). 4.3.2.2 Process Reliability
The SEC (Standard Evaluation Circuit) may be used to qualify the process reliability. The SEC design shall include the basic information described in 3.2.1 to 3.2.1C and shall be submitted to the qualification agency for approval before using the contractor's ordering design specifications. Its manufacturing process is the same as that used to produce any dedicated gate array device to this specification. The SEC shall be designed to evaluate the reliability of the underlying design (diffusion, etc.) and the worst-case conditions of the design rules. The design shall utilize a macrocell library and form an oscillating loop and various test structures that can detect metal-to-metal shorts or opens, high through-hole resistance and dielectric pinholes during reliability life testing. SEC shall be implemented on the largest device (i.e., the device with the largest number of gates in the device category and, if applicable, the device with the largest number of pins in the gate array package). Qualification of the device varieties with the largest number of pins in the contractor's gate array series with fewer gates or the device varieties with fewer pins and fewer gates is carried out in an extended manner (see 4.3.3). SEC is also the primary qualification medium for the following electrical tests (4.4.1, 4.4.2, 4.4.3, 4.4.4). For contractor's SEC requirements, the test limits are specified in the ordering party's design specifications (for minimum requirements for DC parameters, see Table 1 of this specification). The electrical tests for each group are performed as specified in Table 3. When the SEC is subjected to life testing (see 4.4.3), static bias aging shall be applied. 4.3.2.3 The qualification of macrocell design and simulation shall comply with the requirements of A1.5 of Appendix A of Method 5010A of GJB548A. 4.3.2.4CAD wiring and post-wiring simulation
should comply with the requirements of A1.6 in Appendix A of Method 5010A in GJB548A. 4.3.2.5 Verification of design checking software
TTTTKAONrKAca-
④}-input terminal; 0 output terminal: N (M)-the input (output) terminal with the largest number. ③In the case of multiple power supply terminals or multiple block terminals, all power supplies or ground terminals should be connected to the corresponding level. ③The terminal symbol is determined by the user.
Figure 1 Static, dynamic aging and steady-state life test circuit diagram 8-
TTTKAONrKAca
Blue state output test circuit diagram
c. Waveform diagram
SJ20758--1999
Standard output test circuit diagram
Test point
Note: ①C=50pF±10%, including probe and fixture capacitance. Device
-test point
②Input pulse characteristics: 4≤6ns: F1MHz; duty cycle: 50%. ③All unused input terminals are connected to Ypp or GND. @ IThli- ttHL2* tThLi tTlh2- Itlhi= ITlho③S1 is closed during the escape function test and all AC tests (except the output enable test). For the ipzH test, when S2 is connected, S1 and S3 are closed. For the tpzL test, when S3 is connected, SI and S2 are closed. ①For the three-state output, R,=1kQ+10%. For the non-three-state output, Rz is determined by lon under the condition of VoH=2.4V. ③R, is determined by loL (minimum value) at Yn-0.05V minus the current through R to ground, Figure 2 Switching test circuit and waveform diagram
4.3.2.1T. Process control and stability
SJ 20758—1999
The process control and stability of DC parameters must be demonstrated by the contractor and the process monitoring diagram (PM). For testing of DC process parameters (AC parameters can be included at the option of the contractor), PM (or specially inserted or placed in the scribe groove) can be designed in wafer form or packaged device form. PM design should be submitted to the certification body for approval before certification and include at least the following structures: a N-channel device (minimum structure)
b, P-channel device (minimum structure)
N-channel device (large device)
P-channel device (large device)
Sheet resistance test structure
Metal step distribution structure
Field reading value device
h. Intermetallic oxide integrity structure
Connection chain (length should be sufficient to represent contact resistance) (1) Metal to polycrystalline (when applicable)
(2) Channel resistance of metal 1 to metal 2 (when applicable). (3) Inverter chain (for AC testing: determined by the contractor). (4) Metal to diffusion layer (when applicable). For qualification, a minimum of 3 different batches of PMs (4 PMs per wafer) shall be tested to ensure that valid statistics are established and used as a basis for judging whether the contractor's process is stable and controlled. Historical data from the most recent batch may be used to meet this requirement (at the contractor's option). 4.3.2.2 Process Reliability
The SEC (Standard Evaluation Circuit) may be used to qualify the process reliability. The SEC design shall include the basic information described in 3.2.1 to 3.2.1C and shall be submitted to the qualification agency for approval before using the contractor's ordering design specifications. Its manufacturing process is the same as that used to produce any dedicated gate array device to this specification. The SEC shall be designed to evaluate the reliability of the underlying design (diffusion, etc.) and the worst-case conditions of the design rules. The design shall utilize a macrocell library and form an oscillating loop and various test structures that can detect metal-to-metal shorts or opens, high through-hole resistance and dielectric pinholes during reliability life testing. SEC shall be implemented on the largest device (i.e., the device with the largest number of gates in the device category and, if applicable, the device with the largest number of pins in the gate array package). Qualification of the device varieties with the largest number of pins in the contractor's gate array series with fewer gates or the device varieties with fewer pins and fewer gates is carried out in an extended manner (see 4.3.3). SEC is also the primary qualification medium for the following electrical tests (4.4.1, 4.4.2, 4.4.3, 4.4.4). For contractor's SEC requirements, the test limits are specified in the ordering party's design specifications (for minimum requirements for DC parameters, see Table 1 of this specification). The electrical tests for each group are performed as specified in Table 3. When the SEC is subjected to life testing (see 4.4.3), static bias aging shall be applied. 4.3.2.3 The qualification of macrocell design and simulation shall comply with the requirements of A1.5 of Appendix A of Method 5010A of GJB548A. 4.3.2.4CAD wiring and post-wiring simulation
should comply with the requirements of A1.6 in Appendix A of Method 5010A in GJB548A. 4.3.2.5 Verification of design checking software
TTTTKAONrKAca-4CAD wiring and post-wiring simulation
should comply with the requirements of A1.6 in Appendix A of Method 5010A in GJB548A. 4.3.2.5 Verification of design checking software
TTTKAONrKAca-4CAD wiring and post-wiring simulation
should comply with the requirements of A1.6 in Appendix A of Method 5010A in GJB548A. 4.3.2.5 Verification of design checking software
TTTKAONrKAca-
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