SJ 20163-1992 Detailed specification for semiconductor integrated circuit Jμ8086 microprocessor
Some standard content:
Military standard of the electronics industry of the People's Republic of China FL5962
SJ20163--92
Detail specification of Ju8086 microprocessorfor semiconductor integrated circuitsPublished on November 19, 1992
Implementation on May 1, 1993
Approved by the Ministry of Electronics Industry of the People's Republic of China 1 Scope
1.1 Subject content
1.2． Scope
1.3 Classification
2 Reference documents
3 Requirements
Detailed requirements
Design, structure and dimensions
Lead materials and coatings
Electrical characteristics
Electrical test requirements
Microprocessor instruction system…
Division of microcircuit groups
Quality policy and certification regulations
Sampling and inspection…
Identification and inspection
Quality consistency inspection
Inspection method
5 Delivery preparation
5.1 Packaging requirements
6 Notes
General provisions on test vectors
Ordering information
Functional description. Symbols and definitions
Substitution
TYKAONKACa-
People's Republic of China Electronic Industry Military Standard Semiconductor Integrated Circuit
Detail specification of Jμ8086 imicroprocessorfor semiconductor integrated circuits Sub-scope
1.1± Topic content
SJ 20163--92
This specification specifies the detailed requirements for semiconductor integrated circuit Jμ8086 microprocessor (hereinafter referred to as device). 1.2 Scope of application
This specification applies to the development, production and procurement of devices. 1.3 Classification
This specification classifies microcircuits according to device model, device grade, packaging form, rated value and recommended operating conditions. 1.3.1 Device number
The device number should be in accordance with the provisions of Article 3.6.2 of GJB597 "General Specification for Microcircuits". 1.3.1.1 Device Model
The device model is as follows:
Device Model
Ju8086
1.3.1.2 Device Grade
Device Name
16-bit Fixed Instruction Microprocessor
The device grade should be Grade B as specified in Article 3.4 of GJB597 and Grade B1 as specified in this specification. The clauses in this specification that do not specify Grade B1 should be understood as being connected to Grade B. 1.3.1.3 Package Form
The package form is as follows:
Note: 1) According to GB7092 "Outline Dimensions of Semiconductor Integrated Circuits". The Ministry of Electronics Industry of the People's Republic of China issued the package form on November 17, 1992. 1)
D40L3 (40-lead ceramic dual-inline package)
C44P3 (ceramic leadless chip carrier package) was implemented on May 1, 1993.
1.3.2 Absolute maximum ratings
The absolute maximum ratings are as follows:
Power supply voltage
North recommended temperature
Package power dissipation
Device power dissipation
Te=-55 -C
Te=125°C
Lead soldering resistance temperature (5s)
Junction temperature (T=125°℃)
1.3.3 Recommended working conditions
The recommended working conditions are as follows:
Power supply voltage
Input high level voltage
Input low level voltage
Operating frequency
Case operating temperature range
Logic input
Clock input
Logic input
Clock input
Clock rise time (from 1.0V to 3.5V) Clock fall time (from 3.5V to 1.0V) 2 Reference documents
SJ20163—92
GB3431.1—82 Semiconductor integrated Circuit symbols Electrical parameter symbols GB3431.2-86 Semiconductor integrated circuit symbols Terminal function symbols GB4590-84 Conductor integrated circuit mechanical and climatic test methods GB7092 Semiconductor integrated circuit dimensions GJB548-88 Microelectronic device test piece method and procedure GJB597-88 Microcircuit general specification
GJB1649..93 Electronic product anti-static discharge control outline 3 Requirements
3.1 Detailed requirements
TTKAONKAa
SJ20163-92
All requirements shall comply with the provisions of GJB597 and this specification 3.2 Design, structure and dimensions
The design, structure and dimensions shall comply with the provisions of GJB597 and this specification. 3.2.1 Terminal arrangement
The terminal arrangement shall comply with the provisions of Figure 1. The terminal arrangement is a top view. Vss
EFL/57
( tocr
North Genai
National YE Food Association
Vss 20
du Voo
■AD15
37 A17>54
AII>S5
A19-S6
port FES7
HOLD
ALE(QSO)
Dual row pair terminal arrangement
: The maximum mode terminal function (LOCK) is shown in brackets. Figure 1 Pin arrangement
3.2.2 Functional block diagram
The functional diagram is combined with the rules of Figure 2,
INTAQS1)
Execution unit
Register group
Data pointer and
Location register
(8×16)
16-bit arithmetic logic
SJ20163—92
Bus interface unit
Relocation register group
Register group and
Instruction pointer
(5x16)
Bus interface unit
6-byte instruction queue
Control and timing
←←Rest
RESET READY MN/MXV, VoD
Figure 2 Functional block diagram
3.2.3 Functional description, symbols and definitions
Functional description, symbols and definitions shall comply with the provisions of Article 6.3 of this specification. 3.2.4 Package form
The package form shall comply with the provisions of Article 1.3.1.3 of this specification. 3.3 Lead material and coating
Lead material and coating shall comply with the provisions of Article 3.5.6 of GJB597. 3.4 Electrical characteristics
BHE/S?
A16/53~A19/S6
ADD～ADI5
INTA, RD, WR
DTIR, DEN, ALE
>QS. 、QS
TYKAOIKAca-
SJ 20163—92
The output characteristics shall comply with the provisions of Table 1, or there are no other provisions, and are suitable for the entire operating temperature range. 3.5 Electrical test requirements
The electrical test requirements for each level of devices shall be the relevant groups specified in Table 2, and the electrical tests of each group shall be in accordance with the provisions of Table 3. 3.6 Microprocessor instruction system
The microprocessor instruction system shall be in accordance with the provisions of Table 4. 3.7 Marking
The marking shall be in accordance with the provisions of Article 3.6 of GJB597. 3.8 Division of microcircuit groups
The devices involved in this specification are the 107th microcircuit group (see Appendix E of GJB597). Table 1 Electrical characteristics
Input low level voltage (except
CP, MN/MX)
Input high level voltage (except
CP, MN/MX)
Input low voltage at CP
Input high voltage at CP
Input low level at MN/MX
Input high level at MN/MX
Output low level voltage
Output high level voltage
Power supply current
Input low level current
(NMI, INTK, CP,
RESET READY.
TEST MN/MX)
Input high level current
(NMI, INTR, CP,
RESET READY.
TEST, MN/MX)
Input low level current
(ADiI~ADI5)
Input high level current
(ADO~-ADt5)
Bar 3)
Ior=2.0 mA
Use the load in Figure 5
fan-—40U μA
Vop=4.5 V
Use the load in Figure 5
Tc--55 °C
Vpu=5.5 V
Vpp=5.5 V
Specification value
Timing diagram
High impedance leakage current
[A/S, BHE/S7, RD,
DNE(SD), DT/R(ST ),
M/10 (S2 )、WR (1.0CK ))
Input capacitance (all input terminals except ADO~
AD15、LI/)
Input/output capacitance AD
AD15、YAN/GT)
Three-state output capacitance
[A/S、BHE/S7、RD、
DEN(SO)、DT/R(SI)
M/I0(S2)YouR(LOCK )
Clock cycle
Clock low level time
Clock high level time
Data setup time
(to CP falling edge)
Data hold time
(starting from CP falling edge)
Request (RQ/GT) setup time
(to CP rising edge)
State valid delay time [starting from CP,
rising edge (S0~52))
State invalid delay time [starting from CP
falling edge (50~ S2)]
Address valid delay time [starting from CP
falling edge (AD0 ~ ADI5
A16/S3~A19/S6)]
Control valid delay time [starting from
CP Falling edge (BZ/S7
QS1, QSO, LOCK) starts 1
Address invalid delay time [starting from CP
falling edge (AD0 ~ AD15,
A16/S3~A19/S6)
BHE /S7 invalid delay time
(starting from CP falling edge)
twrCE)
SJ 20163---92
Continued Table 1
Condition 3)
VDp=5.5 V
Var-0.45 V
Vpp=5.5 V
Var-2.4 V
Tsuuyi
a(CL-DX)
ISUINOLCHI
Ia.CH-SLi
Id cCE-SHi
fa(CL-AV)
1aicL-OSvi
aL-LUCKYA
faCL-AV)
farCL-BTIEV
Using the load of Figure 6
Specification value
Timing diagram
\, 8, 9,
10，11
10，11
7, 8, 9, 10
11，15
TTKAONKAa-
Address suspension delay time (starting from
CP falling edge)
Data valid delay time [starting from
CP falling edge (AD0~AD15)
State valid delay time [starting from
CP falling edge (/S7.
A16/S3~A19/S6)]
Data invalid delay time [starting from
CP rising edge (AD(～AD15)
State light effect delay time [starting from
CP Starting from the rising edge (BHE/S7,
A16/S3~A10/S6)
R valid delay time (starting from the falling edge of CP
)
RD invalid delay time (starting from the falling edge of CP
)
Response (/) valid delay
time (starting from the falling edge of CP)
Response (R0/GT) invalid delay
time Time (starting from CP falling edge)
SJ20163—92
Continued Table 1
FdrCLA2)
taCLDV)
terCL-SV
T(CH-DZ)
FaiCH-sv)
ta(CL-RL
Fa(C1.-RH)
FarCE-GTL:
tarCL-GTH
Condition 3
Use the load in Figure 6
Keep the signal setup time (to sLIHULDV-Cm)CP rising edge)
The time required to establish asynchronous signals (NMI,
INTR, TEST)
(to CP rising edge)
ALE pulse width
ALE valid delay time (starting from
CP falling edge)
ALE invalid delay time (from
CP Rising edge)
Data valid to WR invalid
(AD0～AD15)
WR, INTA valid delay time
time (starting from CP falling edge)
TsuINMINCHS
aILSIY-CH
fwTALEH)
drCL-ALEH
(d(CH-ALEL)
LarH-n7)
fuCI-NTAL
Specification value
7, 8, 9
7, 8, 9
7，8,9
T/R, M/T valid delay
recession time (starting from CP rising
edge)
Control light effect delay time
(DEN. TNIA, WT)
(starting from CP falling edge)
HLDA valid delay time
(starting from CP falling edge)
DEV valid delay time
(starting from CP rising edge)
Address delay time (starting from CP falling edge)2)
Ready invalid setup time [to
CP (only to T2 state)
SJ 20163—92
Continued Table 1
Condition 3)
Ea(CH·DEV,
tacH-Mrvy
FaICI-DENH
fuCL-INTAH
areL-WH
TaiCL-HLDAV;
IarCH-DENE
fdicL-Av
+sUIREADYL-CL)
Use the load of Figure 6
Specification values
Juice: 1) The serial numbers of the parameters in this specification correspond to the serial numbers of the parameters in the timing diagram. Maximum
Timing Diagram
7,8,10
8,9,10
8, 9, 10
This delay refers to the delay of AD0~AD15, A19/S6~A16/S3, S0~S2, 2)
RD, LOCK and BHE/S7 signal lines during request/response and HOLD/HLDA. 3) If other provisions are met, Vep=5.0V±10%: Tc-55--125°℃: Vs=0V. Table 2 Electrical test requirements
Test requirements
Central South (before aging) electrical test (method 5004) Final electrical test) (method 5004)
A Correction Test Requirements 2) (method 5005)
Group B Vzap test
Group C End-point electrical test (method S005)
Group C test added grouping
Group D End-point electrical test (method 5005)
Class B devices
Sub-groups (now Table 3)
Class B1 devices
A1, A2, A3, A7, A8 A9,
AI, A2, A3, A4, A7, A8,
A9,A10,A11
See Article 4.5.3 of this specification
A2, A3,A8
Not required
A2,A8 (125 °C only)
Method: 1) A1, A7 groups require PDA calculation (see 4.2 of this specification) 2) A4 groups (C, Cc) are only used for identification (see 4.4.1 of this specification). 8-
A1. A2. A3,A7, A9
A1, A2, A3, A4, A7. A9
See 4.5.3 of this specification
A2,A8 (125 °C only)
A，All
A2,A8 (125°C only)
TTKAONKAa-
Group 1)
Waveform
SJ20163—92
Table 3A Group Electrical Test
Tested End
DEN(SO)
DT/R(SI)
M/10($2)
WR(LOCK)
BHE/S?
A19/Sh
A18/S5
A17/S4
A16/S3
(1)Except the tested end, the other terminals are connected to the domain.
(2)When testing one of the tested ends, the terminal is left floating.
(1) When measuring the AD4~AD14 measured terminals, all terminals except these terminals are grounded.
(2) When measuring the ADO ~ AD3, HLDA (RQ/GTI), HOLD (RQ/GTO), and AD15 measured terminals, all terminals except these terminals are grounded.
(3) When measuring any of the measured terminals, the other measured terminals, especially those specified separately, are left floating.
(1)(17, 18, [9) terminals
(2) When measuring one of the measured terminals
, except for this terminal and (17, 18,
19), other terminals are connected
When measuring one of the measured terminals
, this terminal is connected to 0.45V,
Von=5.5 V, Vss-0 V.
Other terminals are left floating.
When measuring one of the measured terminals
, this terminal is connected to 5.5V.
Vpn-5.5 V, Vss-0 V.
Other terminals are left floating.
Specification value 1>4）
Minimum
Group 1
- 10 -
Waveform
DEN(SO)
DT/R(S1)
M/10($2)
WR(LOCK)
BHE/S?
A19/S6
A18/S5
A17/S4
A16/S3
SJ 20163--92
Continued Table 3
(1) The clock pulse level is between
0~0.4V#
(2) When measuring a certain "test terminal", the terminal is connected to 0.45 V,
Ypp=5.5 V, (1, 17.
18, 20, 21, 22, 23, 33) terminals are grounded, and other terminals are suspended
(1) The clock pulse level is between
0 and 0.4 V;
(2) When measuring a certain terminal
, this terminal is connected to 5.5 V, Vpp=
5.5 V, (1, 17, 18,
20, 21, 22, 23, 33) terminals are grounded, and other terminals are suspended
1) The clock pulse level is between
0 and 0.4 V:
(2) When measuring a certain terminal
: this terminal is connected to 0.45 V,
Vpp=5.5 V, (22, 31,
33,) terminals are connected to 3 V, (1~
18, 20, 21, 23, 39)
terminals are grounded, and other terminals are left floating
Specification value 1>4
Minimum maximum
-1010μA
TTTKAONTKAca-(1~
18, 20, 21, 23, 39)
end is grounded, other ends are suspended
Specification value 1>4
Minimum maximum
-1010μA
TTTKAONTKAca-(1~
18, 20, 21, 23, 39)
end is grounded, other ends are suspended
Specification value 1>4
Minimum maximum
-1010μA
TTTKAONTKAca-WT)
(starting from CP falling edge)
HLDA valid delay time
(starting from CP falling edge)
DEV valid delay time
(starting from CP rising edge)
Address delay time (starting from CP
falling edge)2)
Ready invalid setup time [to
CP (only to T2 state)
SJ 20163—92
Continued Table 1
Condition 3)
Ea(CH·DEV,
tacH-Mrvy
FaICI-DENH
fuCL-INTAH
areL-WH
TaiCL-HLDAV;
IarCH-DENE
fdicL-Av
+sUIREADYL-CL)
Use the load of Figure 6
Specification values
Juice: 1) The serial numbers of the parameters in this specification correspond to the serial numbers of the parameters in the timing diagram. Maximum
Timing Diagram
7,8,10
8,9,10
8, 9, 10
This delay refers to the delay of AD0~AD15, A19/S6~A16/S3, S0~S2, 2)
RD, LOCK and BHE/S7 signal lines during request/response and HOLD/HLDA. 3) If other provisions are met, Vep=5.0V±10%: Tc-55--125°℃: Vs=0V. Table 2 Electrical test requirements
Test requirements
Central South (before aging) electrical test (method 5004) Final electrical test) (method 5004) bzxz.net
A Correction Test Requirements 2) (method 5005)
Group B Vzap test
Group C End-point electrical test (method S005)
Group C test added grouping
Group D End-point electrical test (method 5005)
Class B devices
Sub-groups (now Table 3)
Class B1 devices
A1, A2, A3, A7, A8 A9,
AI, A2, A3, A4, A7, A8,
A9,A10,A11
See Article 4.5.3 of this specification
A2, A3,A8
Not required
A2,A8 (125 °C only)
Method: 1) A1, A7 groups require PDA calculation (see 4.2 of this specification) 2) A4 groups (C, Cc) are only used for identification (see 4.4.1 of this specification). 8-
A1. A2. A3,A7, A9
A1, A2, A3, A4, A7. A9
See 4.5.3 of this specification
A2,A8 (125 °C only)
A，All
A2,A8 (125°C only)
TTKAONKAa-
Group 1)
Waveform
SJ20163—92
Table 3A Group Electrical Test
Tested End
DEN(SO)
DT/R(SI)
M/10($2)
WR(LOCK)
BHE/S?
A19/Sh
A18/S5
A17/S4
A16/S3
(1)Except the tested end, the other terminals are connected to the domain.
(2)When testing one of the tested ends, the terminal is left floating.
(1) When measuring the AD4~AD14 measured terminals, all terminals except these terminals are grounded.
(2) When measuring the ADO ~ AD3, HLDA (RQ/GTI), HOLD (RQ/GTO), and AD15 measured terminals, all terminals except these terminals are grounded.
(3) When measuring any of the measured terminals, the other measured terminals, especially those specified separately, are left floating.
(1)(17, 18, [9) terminals
(2) When measuring one of the measured terminals
, except for this terminal and (17, 18,
19), other terminals are connected
When measuring one of the measured terminals
, this terminal is connected to 0.45V,
Von=5.5 V, Vss-0 V.
Other terminals are left floating.
When measuring one of the measured terminals
, this terminal is connected to 5.5V.
Vpn-5.5 V, Vss-0 V.
Other terminals are left floating.
Specification value 1>4）
Minimum
Group 1
- 10 -
Waveform
DEN(SO)
DT/R(S1)
M/10($2)
WR(LOCK)
BHE/S?
A19/S6
A18/S5
A17/S4
A16/S3
SJ 20163--92
Continued Table 3
(1) The clock pulse level is between
0~0.4V#
(2) When measuring a certain "test terminal", the terminal is connected to 0.45 V,
Ypp=5.5 V, (1, 17.
18, 20, 21, 22, 23, 33) terminals are grounded, and other terminals are suspended
(1) The clock pulse level is between
0 and 0.4 V;
(2) When measuring a certain terminal
, this terminal is connected to 5.5 V, Vpp=
5.5 V, (1, 17, 18,
20, 21, 22, 23, 33) terminals are grounded, and other terminals are suspended
1) The clock pulse level is between
0 and 0.4 V:
(2) When measuring a certain terminal
: this terminal is connected to 0.45 V,
Vpp=5.5 V, (22, 31,
33,) terminals are connected to 3 V, (1~
18, 20, 21, 23, 39)
terminals are grounded, and other terminals are left floating
Specification value 1>4
Minimum maximum
-1010μA
TTTKAONTKAca-WT)
(starting from CP falling edge)
HLDA valid delay time
(starting from CP falling edge)
DEV valid delay time
(starting from CP rising edge)
Address delay time (starting from CP
falling edge)2)
Ready invalid setup time [to
CP (only to T2 state)
SJ 20163—92
Continued Table 1
Condition 3)
Ea(CH·DEV,
tacH-Mrvy
FaICI-DENH
fuCL-INTAH
areL-WH
TaiCL-HLDAV;
IarCH-DENE
fdicL-Av
+sUIREADYL-CL)
Use the load of Figure 6
Specification values
Juice: 1) The serial numbers of the parameters in this specification correspond to the serial numbers of the parameters in the timing diagram. Maximum
Timing Diagram
7,8,10
8,9,10
8, 9, 10
This delay refers to the delay of AD0~AD15, A19/S6~A16/S3, S0~S2, 2)
RD, LOCK and BHE/S7 signal lines during request/response and HOLD/HLDA. 3) If other provisions are met, Vep=5.0V±10%: Tc-55--125°℃: Vs=0V. Table 2 Electrical test requirements
Test requirements
Central South (before aging) electrical test (method 5004) Final electrical test) (method 5004)
A Correction Test Requirements 2) (method 5005)
Group B Vzap test
Group C End-point electrical test (method S005)
Group C test added grouping
Group D End-point electrical test (method 5005)
Class B devices
Sub-groups (now Table 3)
Class B1 devices
A1, A2, A3, A7, A8 A9,
AI, A2, A3, A4, A7, A8,
A9,A10,A11
See Article 4.5.3 of this specification
A2, A3,A8
Not required
A2,A8 (125 °C only)
Method: 1) A1, A7 groups require PDA calculation (see 4.2 of this specification) 2) A4 groups (C, Cc) are only used for identification (see 4.4.1 of this specification). 8-
A1. A2. A3,A7, A9
A1, A2, A3, A4, A7. A9
See 4.5.3 of this specification
A2,A8 (125 °C only)
A，All
A2,A8 (125°C only)
TTKAONKAa-
Group 1)
Waveform
SJ20163—92
Table 3A Group Electrical Test
Tested End
DEN(SO)
DT/R(SI)
M/10($2)
WR(LOCK)
BHE/S?
A19/Sh
A18/S5
A17/S4
A16/S3
(1)Except the tested end, the other terminals are connected to the domain.
(2)When testing one of the tested ends, the terminal is left floating.
(1) When measuring the AD4~AD14 measured terminals, all terminals except these terminals are grounded.
(2) When measuring the ADO ~ AD3, HLDA (RQ/GTI), HOLD (RQ/GTO), and AD15 measured terminals, all terminals except these terminals are grounded.
(3) When measuring any of the measured terminals, the other measured terminals, especially those specified separately, are left floating.
(1)(17, 18, [9) terminals
(2) When measuring one of the measured terminals
, except for this terminal and (17, 18,
19), other terminals are connected
When measuring one of the measured terminals
, this terminal is connected to 0.45V,
Von=5.5 V, Vss-0 V.
Other terminals are left floating.
When measuring one of the measured terminals
, this terminal is connected to 5.5V.
Vpn-5.5 V, Vss-0 V.
Other terminals are left floating.
Specification value 1>4）
Minimum
Group 1
- 10 -
Waveform
DEN(SO)
DT/R(S1)
M/10($2)
WR(LOCK)
BHE/S?
A19/S6
A18/S5
A17/S4
A16/S3
SJ 20163--92
Continued Table 3
(1) The clock pulse level is between
0~0.4V#
(2) When measuring a certain "test terminal", the terminal is connected to 0.45 V,
Ypp=5.5 V, (1, 17.
18, 20, 21, 22, 23, 33) terminals are grounded, and other terminals are suspended
(1) The clock pulse level is between
0 and 0.4 V;
(2) When measuring a certain terminal
, this terminal is connected to 5.5 V, Vpp=
5.5 V, (1, 17, 18,
20, 21, 22, 23, 33) terminals are grounded, and other terminals are suspended
1) The clock pulse level is between
0 and 0.4 V:
(2) When measuring a certain terminal
: this terminal is connected to 0.45 V,
Vpp=5.5 V, (22, 31,
33,) terminals are connected to 3 V, (1~
18, 20, 21, 23, 39)
terminals are grounded, and other terminals are left floating
Specification value 1>4
Minimum maximum
-1010μA
TTTKAONTKAca-0V±10%: Tc-55--125°℃: Vs=0V. Table 2 Electrical test requirements
Test requirements
Central South (before aging) electrical test (method 5004) Final electrical test) (method 5004)
A Correction Test Requirements 2) (method 5005)
Group B Vzap test
Group C End-point electrical test (method S005)
Group C test added grouping
Group D End-point electrical test (method 5005)
Class B devices
Sub-groups (now Table 3)
Class B1 devices
A1, A2, A3, A7, A8 A9,
AI, A2, A3, A4, A7, A8,
A9,A10,A11
See Article 4.5.3 of this specification
A2, A3,A8
Not required
A2,A8 (125 °C only)
Method: 1) A1, A7 groups require PDA calculation (see 4.2 of this specification) 2) A4 groups (C, Cc) are only used for identification (see 4.4.1 of this specification). 8-
A1. A2. A3,A7, A9
A1, A2, A3, A4, A7. A9
See 4.5.3 of this specification
A2,A8 (125 °C only)
A，All
A2,A8 (125°C only)
TTKAONKAa-
Group 1)
Waveform
SJ20163—92
Table 3A Group Electrical Test
Tested End
DEN(SO)
DT/R(SI)
M/10($2)
WR(LOCK)
BHE/S?
A19/Sh
A18/S5
A17/S4
A16/S3
(1)Except the tested end, the other terminals are connected to the domain.
(2)When testing one of the tested ends, the terminal is left floating.
(1) When measuring the AD4~AD14 measured terminals, all terminals except these terminals are grounded.
(2) When measuring the ADO ~ AD3, HLDA (RQ/GTI), HOLD (RQ/GTO), and AD15 measured terminals, all terminals except these terminals are grounded.
(3) When measuring any of the measured terminals, the other measured terminals, especially those specified separately, are left floating.
(1)(17, 18, [9) terminals
(2) When measuring one of the measured terminals
, except for this terminal and (17, 18,
19), other terminals are connected
When measuring one of the measured terminals
, this terminal is connected to 0.45V,
Von=5.5 V, Vss-0 V.
Other terminals are left floating.
When measuring one of the measured terminals
, this terminal is connected to 5.5V.
Vpn-5.5 V, Vss-0 V.
Other terminals are left floating.
Specification value 1>4）
Minimum
Group 1
- 10 -
Waveform
DEN(SO)
DT/R(S1)
M/10($2)
WR(LOCK)
BHE/S?
A19/S6
A18/S5
A17/S4
A16/S3
SJ 20163--92
Continued Table 3
(1) The clock pulse level is between
0~0.4V#
(2) When measuring a certain "test terminal", the terminal is connected to 0.45 V,
Ypp=5.5 V, (1, 17.
18, 20, 21, 22, 23, 33) terminals are grounded, and other terminals are suspended
(1) The clock pulse level is between
0 and 0.4 V;
(2) When measuring a certain terminal
, this terminal is connected to 5.5 V, Vpp=
5.5 V, (1, 17, 18,
20, 21, 22, 23, 33) terminals are grounded, and other terminals are suspended
1) The clock pulse level is between
0 and 0.4 V:
(2) When measuring a certain terminal
: this terminal is connected to 0.45 V,
Vpp=5.5 V, (22, 31,
33,) terminals are connected to 3 V, (1~
18, 20, 21, 23, 39)
terminals are grounded, and other terminals are left floating
Specification value 1>4
Minimum maximum
-1010μA
TTTKAONTKAca-0V±10%: Tc-55--125°℃: Vs=0V. Table 2 Electrical test requirements
Test requirements
Central South (before aging) electrical test (method 5004) Final electrical test) (method 5004)
A Correction Test Requirements 2) (method 5005)
Group B Vzap test
Group C End-point electrical test (method S005)
Group C test added grouping
Group D End-point electrical test (method 5005)
Class B devices
Sub-groups (now Table 3)
Class B1 devices
A1, A2, A3, A7, A8 A9,
AI, A2, A3, A4, A7, A8,
A9,A10,A11
See Article 4.5.3 of this specification
A2, A3,A8
Not required
A2,A8 (125 °C only)
Method: 1) A1, A7 groups require PDA calculation (see 4.2 of this specification) 2) A4 groups (C, Cc) are only used for identification (see 4.4.1 of this specification). 8-
A1. A2. A3,A7, A9
A1, A2, A3, A4, A7. A9
See 4.5.3 of this specification
A2,A8 (125 °C only)
A，All
A2,A8 (125°C only)
TTKAONKAa-
Group 1)
Waveform
SJ20163—92
Table 3A Group Electrical Test
Tested End
DEN(SO)
DT/R(SI)
M/10($2)
WR(LOCK)
BHE/S?
A19/Sh
A18/S5
A17/S4
A16/S3
(1)Except the tested end, the other terminals are connected to the domain.
(2)When testing one of the tested ends, the terminal is left floating.
(1) When measuring the AD4~AD14 measured terminals, all terminals except these terminals are grounded.
(2) When measuring the ADO ~ AD3, HLDA (RQ/GTI), HOLD (RQ/GTO), and AD15 measured terminals, all terminals except these terminals are grounded.
(3) When measuring any of the measured terminals, the other measured terminals, especially those specified separately, are left floating.
(1)(17, 18, [9) terminals
(2) When measuring one of the measured terminals
, except for this terminal and (17, 18,
19), other terminals are connected
When measuring one of the measured terminals
, this terminal is connected to 0.45V,
Von=5.5 V, Vss-0 V.
Other terminals are left floating.
When measuring one of the measured terminals
, this terminal is connected to 5.5V.
Vpn-5.5 V, Vss-0 V.
Other terminals are left floating.
Specification value 1>4）
Minimum
Group 1
- 10 -
Waveform
DEN(SO)
DT/R(S1)
M/10($2)
WR(LOCK)
BHE/S?
A19/S6
A18/S5
A17/S4
A16/S3
SJ 20163--92
Continued Table 3
(1) The clock pulse level is between
0~0.4V#
(2) When measuring a certain "test terminal", the terminal is connected to 0.45 V,
Ypp=5.5 V, (1, 17.
18, 20, 21, 22, 23, 33) terminals are grounded, and other terminals are suspended
(1) The clock pulse level is between
0 and 0.4 V;
(2) When measuring a certain terminal
, this terminal is connected to 5.5 V, Vpp=
5.5 V, (1, 17, 18,
20, 21, 22, 23, 33) terminals are grounded, and other terminals are suspended
1) The clock pulse level is between
0 and 0.4 V:
(2) When measuring a certain terminal
: this terminal is connected to 0.45 V,
Vpp=5.5 V, (22, 31,
33,) terminals are connected to 3 V, (1~
18, 20, 21, 23, 39)
terminals are grounded, and other terminals are left floating
Specification value 1>4
Minimum maximum
-1010μA
TTTKAONTKAca-
Leave the other terminals floating.
Specification value 1>4）
Minimum
Group 1
- 10 -
Waveform
DEN(SO)
DT/R(S1)
M/10($2)
WR(LOCK)
BHE/S?
A19/S6
A18/S5
A17/S4
A16/S3
SJ 20163--92
Continued Table 3
(1) The clock pulse level is between
0~0.4V#
(2) When measuring a certain "test terminal", the terminal is connected to 0.45 V,
Ypp=5.5 V, (1, 17.
18, 20, 21, 22, 23, 33) terminals are grounded, and other terminals are suspended
(1) The clock pulse level is between
0 and 0.4 V;
(2) When measuring a certain terminal
, this terminal is connected to 5.5 V, Vpp=
5.5 V, (1, 17, 18,
20, 21, 22, 23, 33) terminals are grounded, and other terminals are suspended
1) The clock pulse level is between
0 and 0.4 V:
(2) When measuring a certain terminal
: this terminal is connected to 0.45 V,
Vpp=5.5 V, (22, 31,
33,) terminals are connected to 3 V, (1~
18, 20, 21, 23, 39)
terminals are grounded, and other terminals are left floating
Specification value 1>4
Minimum maximum
-1010μA
TTTKAONTKAca-
Leave the other terminals floating.
Specification value 1>4）
Minimum
Group 1
- 10 -
Waveform
DEN(SO)
DT/R(S1)
M/10($2)
WR(LOCK)
BHE/S?
A19/S6
A18/S5
A17/S4
A16/S3
SJ 20163--92
Continued Table 3
(1) The clock pulse level is between
0~0.4V#
(2) When measuring a certain "test terminal", the terminal is connected to 0.45 V,
Ypp=5.5 V, (1, 17.
18, 20, 21, 22, 23, 33) terminals are grounded, and other terminals are suspended
(1) The clock pulse level is between
0 and 0.4 V;
(2) When measuring a certain terminal
, this terminal is connected to 5.5 V, Vpp=
5.5 V, (1, 17, 18,
20, 21, 22, 23, 33) terminals are grounded, and other terminals are suspended
1) The clock pulse level is between
0 and 0.4 V:
(2) When measuring a certain terminal
: this terminal is connected to 0.45 V,
Vpp=5.5 V, (22, 31,
33,) terminals are connected to 3 V, (1~
18, 20, 21, 23, 39)
terminals are grounded, and other terminals are left floating
Specification value 1>4
Minimum maximum
-1010μA
TTTKAONTKAca-
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