This standard specifies the logical functions, external lead arrangement and main electrical parameters of semiconductor integrated circuit ECL circuit series and varieties. GB/T 3434-1986 Semiconductor integrated circuit ECL circuit series and varieties GB/T3434-1986 Standard download decompression password: www.bzxz.net

National Standard of the People's Republic of China
Families and products
of EcLcircuitsfor semiconductorintegrated circuitsUDC 621.382.049
.75-181.4
GB3434—8.6
CB334-82
This standard specifies the logical functions, external lead arrangement and important capacitance of the series and varieties of semiconductor integrated circuits (ECL) (hereinafter referred to as devices). When producing (developing) or selecting devices, their series and varieties shall comply with the provisions of this standard. This standard is formulated with reference to the internationally used FCL series and varieties. If otherwise specified, the logic involved in this standard is positive logic. 「Symbols and codes
1.1 The meanings of the logical graphic symbols used in this standard are shown in Appendix A (Supplement), and the meanings of the text symbols used are shown in Appendix B (Supplement).
1.2 The device types, series and varieties listed in this standard are coded as the varieties of the 2CE10000 series of device models
Device name
Four 2-input OR/NOR gate" (with common input terminal) Three 2, 3, 2-input OR/NOR gate"
Dual 4, 5-input OR OR gate
Dual 3-input OR/NOR gate" (two OR output terminals) Four 2-input OR gate (-gate with OR output terminal) 54, 3, 3-input OR NOR gate
Dual 3-input OR NOR gate: (one output terminal) Dual 3-input OR gate (three output terminals)
Four 2-input gate (one gate with NAND output terminal) Dual 2-way 2 3-input OR OR NAND gate
4-way-33-input OR gate OR NAND gate
Dual 2-way 3--3-input OR AND gate
4-way 4 — 3 — 3 — 3 input OR AND gate driver and receiver
Six 2-input OR/buffer solution (with public input terminal) Four-edge receiver
Three-wire receiver
Three-wire receiver
Electro-optical converter
Quad TI-electrical semi-converter (with public input terminal) Quad EC1.TT1, electro-optical semi-converter
National Bureau of Standards 1986-04-02 issued
Part,
Type, series variety code
CE10105
CF10109||tt ||CE10212
CE10102
CE10106
CE10110
CE10104
CE101?
CE10118
.C E10119
CE10195
CE10115
CE1D116
CE10216
CE1D124
CH10125
1986 12 01 Implementation
Device Name
Triple ECL: NMOS Level Converter
Flip Flops and Latches
Dual Master-Slave \\-K Flip Flops
Dual Master-Slave D Flip Flops
Dual Master-Slave D Flip Flops
Six Master-Slave D Flip Flops (Q Output)
Dual D Latch
Quadruple D Latch
Quadruple D Latch (Negative Clock)
Five D Latch
Arithmetic Unit
Dual 200 Million Adder/Subtractor
4-bit Arithmetic Inversion Unit/Function Generator
Carry Lookahead Generator
2 Bit × 1 tt||5-bit multiplier
5-bit value comparator
9-bit parity checker/generator
12-bit parity checker/generator
Hamming error detection/correction circuit
Three 2-input XOR/XN gates
Four 2-input XOR gates (with common enable terminal) register
8×2-bit 2-way register array
4-bit shift register
Priority encoder
8-line to 3-line optimal optical encoder (register output) data selector
8 to 1 data selector
Dual 4 to 1 Data selector
4-bit 2-to-1 data selector (register output)Double 2-to-1 data selector (register output)Double 2-to-1 data selector (register output)Quadruple 2-to-1 data selector
GB3434-86
Quadruple 2-to-1 data selector (inverted output, with enable input)Decoder
3-line to 8-line decoder (decoding output is "1.\)3-line to 8-line decoder
Double 2-line to 4-line decoder (with public address input, decoding output is "\)Double 2-line to 4-line decoder (with public address input)Counter
Decade counter
4 4-bit binary counter
4-bit unary ripple counter
Type, series and variety code
CE10177
CE10135
CE10131
CE10231
CE10176
CH10130
CF10133
CE10153
C E10175
CF:10180
CF10181
CE10179
CF10287
CE10166|| tt||CE10160
CE1163
CEE0107
CE10113
CE10143
CE10141
CF10165
CE10164
CE10t74
CE10173
CE10132
CE1 0134
CE10158
CE10159
CE10161
CE10162
CE10171
CE10172
CH1U137
CE10136
CE1017H
GB3434—B6
2.1 Four 2-input OR/NOR gate (with common input terminal) 2.1.1 Logic diagram
CE10101
2.1.2 Logical expression
2.1.3 External lead arrangement
VcC2 4F 3Y4AB
国国国国国心
Veeriy
2.1.#Main electrical parameters (typical values)
2.1.5Recommended circuit
Pn=100mW
:2,3,2 input OR/NOR gate
2.2.1Logic diagram
GB3484-86
CE10105
2A 2# 2℃
2.2.2Logic type
Y=A+B+(C)
2.2.3Outer lead arrangement
-A+B+GT
'ec2 3F 3F :
国国国国
0Ou0gda
IB2F2Y
Kerr Iy
2.2.4 Main electrical parameters (typical values)
Ipd=2.0ns
2.2.5 Recommended circuit
Pp= 90mW
GB 3434--86
2.# Dual 4, 5 input OR/NOR gate
CE10109
2.3.1 Logic diagram
1AIR1G1
2.8.2 Logical expression
2A23203
Y=A+R+C+D+(F)
2.3.3 External lead arrangement
Y-AIB-C+D+(F
WeC 2Y 2y 242R
6[15413]]
Vcc {FI ℃
2..4 Main electrical parameters (typical values)
fpd= 2.0ns
2.8.5Recommended circuit
P-60nW
GB 3434—86
2.4 Dual 3-input OR/NOR gate (two OR/N output terminals) CE102122.1 Logic diagram
Iy, iy, iy 2y,2 2y
IAIBIC
2.4.2 Logical expression
Y=A+B+C
2.4.3 External lead arrangement
2A2R20
Y-A+B+C
Vec Vect 2F 27, 27
2℃ 2B 2A
s45 g
1Y11A18
Kcei iy
2.4.4 Main electrical parameters (typical values)
trd - 1.5ns
2.4.5 Recommended circuit
Pn=160mw
GB3434--86
2.5 Four 2-input NOR gate (one gate has OR output terminal) 2.5.1 Logic diagram
CE10102
Zhongzhong Zhongying
2.5.2 Logical expression
2.5.3 External lead arrangement
16514 2 1 09
0234678
2.5.4 Main electrical parameters (typical values)
2.5.5 Recommended circuit
Py= 100mw
GB 3434—86
2.6 4, 3, 3 input NOR gate CE10106 2.6.1 Logic diagram
IAIRICD
2.6.2 Logical expression
24 2B 2℃:
YA-H+C+(D)
“External lead data list
Vecasy
国国aeaee
O2E4GGO
Vect 2F1 1A 15 IG
2.6.4 ± Electrical parameters (typical values)
trd= 2.0ns
2.6.5 Lead wire arrangement
Pn=90mW
'cVocs
2.7 Dual 3-input NOR gate (three output terminals) 2.7.1 Logic diagram
GB 343--86
CF10111
1F1F 1 2123a2
Logic expression
2.4 2H 2C
Y-A+R+C
3 External lead arrangement
Vcc2 Vrci 2V 2Yg 2Y, 2℃
Main electrical parameters (typical values)
tpa= 2.4ns
2.7.5 Recommended circuit
Pp=150mW
2.8 Dual 3-input OR gate (three output terminals) 2.8.1 Logic diagram
Logic expression
2.8.3 External lead arrangement
GB3434—86.
Iy,JYa1Ye 2V,2Y,2Y
2.4 28 2L
Y=A+B+C
Vecr +'cer 2Ye 2ra 2r+
Vcct IYA TY IYe TA
+Electrical parameters (typical values)
trd - 2.4ns
Recommended circuit
Pμ= 160mw
GB 3434—86
2.9 Four 2-input AND gate (gate with NAND output terminal) CE10104
2.9.1 Logic diagram
1A1W2A2B
34 3月444月
2.$.2 Logical expression
Y=A·B
2.9.3 External lead arrangement
134568
VCC1Y2YIAIR2A2B
2.9.4 Main electrical parameters (typical values)
2.9.5 Recommended circuit
Pμ= 140mWbzxz.net
GB 3484—86
2.10 Dual 2-way 2-3 input OR and gate CF101172.10.1 Logic diagram
A18 1℃
Logical expression
Y- (A+B).C+D+E)
2.10.3 External lead arrangement
VcC2Y2Y
2 2 2R 2.4
Y-{A+B).(C+D+E)
2.10.4 Main electrical parameters (typical values)
tpd=2.3ns
2.10.5 Recommended circuit
tyVecs
Pn- 100mW3 External lead arrangement
134568
VCC1Y2YIAIR2A2B
2.9.4 Main electrical parameters (typical values)
2.9.5 Recommended circuit
Pμ= 140mW
GB 3484—86
2.10 Dual 2-way 2-3 input OR and; OR and finger gate CF101172.10.1 Logic diagram
A18 1℃
Logical expression
Y- (A+B).C+D+E)
2.10.3 External lead arrangement
VcC2Y2Y
2 2 2R 2.4
Y-{A+B).(C+D+E)
2.10.4Main electrical parameters (typical values)
tpd=2.3ns
2.10.5Recommended circuit
tyVecs
Pn- 100mW3 External lead arrangement
134568
VCC1Y2YIAIR2A2B
2.9.4 Main electrical parameters (typical values)
2.9.5 Recommended circuit
Pμ= 140mW
GB 3484—86
2.10 Dual 2-way 2-3 input OR and; OR and finger gate CF101172.10.1 Logic diagram
A18 1℃
Logical expression
Y- (A+B).C+D+E)
2.10.3 External lead arrangement
VcC2Y2Y
2 2 2R 2.4
Y-{A+B).(C+D+E)
2.10.4Main electrical parameters (typical values)
tpd=2.3ns
2.10.5Recommended circuit
tyVecs
Pn- 100mW
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