SJ 20279-1993 Semiconductor integrated circuits JT54LS08, JT54LS09, JT54LS11, JT54LS15, JT54LS21 LS-TTL AND gate detailed specification
Some standard content:
FL5962 Military Standard for Electronic Industry of the People's Republic of China
Semiconductor Integrated Circuits
SJ20279—93
Detail specification for types JT54LS08. JT54LS09.JT54LS11- JT54LS15 and JT54LS21 AND gatesof LS-TTL semiconductor integrated circuitsPublished on 11 May 1993
Implemented on 1 July 1993
Published by the Ministry of Machinery and Electronics Industry of the People's Republic of China 1 Fan Yan
1.1 Subject Content·
1.2 Applicable standards
1.3 Classification...
2 Reference documents
3 Requirements
3.1 Detailed requirements
3.2 Design, structure and dimensions..
3.3 Lead materials and coating
3.4 Electrical characteristics
Electrical test requirements
Division of microcircuit groups
Quality assurance regulations
Sampling and inspection
Identification inspection
Quality consistency inspection
Inspection methods|| tt||5 Delivery preparation
5.1 Packaging requirements
6 Notes
6.1 Ordering information
Abbreviations, symbols and definitions
Substitution
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People's Republic of China Electronic Industry Military Standard Semiconductor Integrated Circuits
JT54LS08, JT54LS09, JT54LS11, JT54LS15, JT54LS21 LSTTL AND Gate Detailed Specifications
Detail specification for types JT541.S08, JT54LS09, JT54LS11, JT54LS15 and JT54LS21 AND gates
of LS-TTL semiconductor integrated circuits 1 Scope
1. 1 Subject matter
SJ 20279---93
This specification specifies the detailed requirements for silicon monolithic JT54LS08, JT54LS09, JT54LS11, JT54LS15 and JT54LS21 LS-TTL AND gates (hereinafter referred to as devices). 1.2 Applicability
This specification applies to the development, production and procurement of devices: 1.3 Classification
The devices given in this specification are classified according to device model, device grade, packaging form, rated value and recommended operating conditions. 1.3.1 Device numbering
The device numbering shall comply with the provisions of Article 3 and 6.2 of GJB597 Microcircuit General Specification and this specification. 1.3.1.1 Device model
The device models are as follows:
Device model
JT54LS08
JT54LS09
JTS4LS11
JT54LS15
JT54LS21
Quad 2-input AND gate
Quad 2-input AND gate (OC)
Triple 3-input AND gate
Double 4-input AND gate
1993-05-11 Ministry of Machinery and Electronics Industry of the People's Republic of China Approved the device name
1993-07-01 Implementation||t t||1.3.1.2 Device grade
SJ20279-93
The device grade is B grade specified in Article 3.4 of G.FB597 and B1 grade specified in this specification. 1.3.1.3 Package form
The package forms are as follows:
Package form\
C20P3 (ceramic integrated circuit carrier package)D14S3 (ceramic dual-row package)
FI14X2 (ceramic flat package)
H14X2 (ceramic fused seal fan seal)
J14S3 (ceramic olefin seal dual-row package)
Note: 1) According to GB7092 "Semiconductor Integrated Circuit Outline Dimensions". 1.3.2 Absolute Maximum Ratings
The absolute maximum ratings are as follows:
Power Supply Voltage
Input Voltage
Storage Temperature
Wire Resistance to Soldering Temperature (10 s)
JT54LS11
JT54LS15
JT54LS21
JI541.S08
JT54LS9
Note: 1) The added voltage during the performance test c is 1. 3. 3 Working conditions
The recommended working conditions are as follows
Power supply voltage
Input high level voltage
Input low level voltage
Output standby voltage
Hanshan City Self-driving Current
FI54LS09
JT54LS15
JT541.S08
r54LS11
JT54LS21
Vororr
Specification value
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Input low level current
Working environment tolerance
2 Reference documents
SJ 20279—93
Specification value
2 Semiconductor integrated circuit symbol Electrical parameter Symbol GB 3431.1—82
GB3431.2—86 Semiconductor integrated circuit text symbol terminal function symbol maximum
GB3439--82 Basic principles of semiconductor integrated circuit TTL circuit test methods GB4590—84 Mechanical and climatic test methods for semiconductor integrated circuits GB4728.12-85 Graphic symbols for electrical diagrams Binary logic units, Semiconductor integrated circuit dimensions
GB 7092—93
GJB548-88 Test methods and procedures for microelectronic devices GJB59788 General specification for microcircuits
GJR/7.105 Manual requirements for anti-static discharge control of electronic products
3.tDetailed requirements
All requirements shall be in accordance with the provisions of GJB597 and this specification. 3.2 Design, structure and dimensions
The design, structure and dimensions shall be in accordance with the provisions of GJB597 and this specification. 3.2.1Logical symbols, logic diagrams and lead-out arrangement list
Logical symbols, logic diagrams and lead-out arrangement shall comply with the provisions of Figure 1. The lead-out arrangement is a top view. 3.2.2Function table
The function table is as follows:
JT54LS08., JT54LS09
JT54LS11, JT54LS15
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JT54LS21
Note: H—high level L——low level.
3.2.3Electrical schematic diagram
The manufacturer shall submit the electrical schematic diagram to the appraisal agency before appraisal. The electrical schematic diagram of each manufacturer shall be filed by the appraisal agency for future reference.
3.2.4Packaging form
The packaging form shall comply with the provisions of Article 1.3.1.3 of this specification. 3.3 Lead materials and coating
Lead materials and coating shall comply with the provisions of GJB597 Section 3.5.6.4-color characteristics
Electrical characteristics are as specified in Table 1,
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JT54LS08
Reverse symbol
JT54LS09
Compliance diagram
Compliance symbol
Logical diagram
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Terminal arrangement
D, F, H, type
14 uee
910111213
Pin-out arrangement
D, F, H, J type
14:38
910111213/
JT54LS11
Logic diagram
JT54LS15
Edit symbol
Logic diagram
SJ 20279—93
D, F, H, J type
Pin-out arrangement
130 1C
D, F, H, J type
Go cir
2 20 19
9 10111213/
Pin-out arrangement
tap vee
3 21 20 19
14 58
10111213
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JT54I.S21
Logic symbol
Logic window
SJ 20279—93
D, F, H, J type
Pin-out arrangement
14pVce
21 20 19
18#2℃
9 10 1112134
Figure 1 Logic symbol, logic diagram and pin arrangement Table 1-1 Output characteristics of JT54LS08
Input high voltage
Output low voltage
Input bit voltage
Maximum input voltage Input current
Input high current
Input low current
Output current 2)
Output level supply current
Input low level supply current
Output high to low level transmission delay time Output low to high level transmission delay time
Note: 1) The complete test conditions are listed in Table 3. 2) Only short-circuit one input terminal at a time,
(If other requirements are specified
-55 °C≤T≤125°℃)
Vcc-4.5 V, Vrn-2.0 V
loH--400 μA
Vcc=4.5 V. lor.=4 mA,
Vit=0.7 V
Kar:-4.5 V, fk—18 mA
T, =25 °C
Yc=5.5 V. Ve-7.1 V
Ves-5.5 V, V=2.7 V
Vcc=5.5 V, V-0.4 V
Vec-5.5 V, f-4.5 v
Vcc-5.5 V, V,=0 V
Vcc-5.0 V, Ci.-15 pF*
Rt=2 ko2
Vce-5.0 V, Gt-1s pF
R-2 k2
Specification value
Output standby voltage
Input pin position
Output cut-off current
Maximum input current
Input high current
Input low current
Input high supply current
Output low supply current
Output high to low transmission delay time
Input low to off-level transmission delay time SJ 20279--.93
Table 1-2 Electrical characteristics of T54LS09
THROFE)
Juice: 1) The complete test conditions are listed in Table 3 (if specified
-55 °CTA125 2C)
Icr=4.5 V, fnr=4 mA.
Vcc=4.5 V, fik=-18 mA
TA=25°C
Ycr-4.5 V, Vm=2.0 V
Vcc=5.5 V, Vi-7.0 V
Ycc=5.5 V, It-2.7 V
Ycc-5.5 V, V-0.4 V
Veu-5.5 V. V-4.5 V
Vcs-5.5 V, Y-0 V
Vcc=5.0 V, C -15 pF
Ri=2 kn2
Vox=5.0 V, Gt=15 pF
Table 13 Electrical characteristics of JT54LS11
Except 1
Output high level voltage
Output low level
Input rated voltage
Input current at maximum input voltage
Input rated current
Input low current
Input current 2
Input high level supply current
Input source current
Transmission delay from high level to low level 8
(Unless otherwise specified
-55 CTA3125 \C)
Vcc=4.5 V, Vir=2.0 V
JOH--400μA
Ycc4.5 V, Iol=4 mA,
YiL-0.7 V
Ycc-4.5 V. Iik--18 mA
TA=25°C
Yc5.5 V, V-7.0 V
Veco=5.5 V, V-2.7 V
Vec-5.5 V, V:=-0.4 V
Vcc=5.5 V, Vip-4.5 V
Vec-5.5 V, F-0 V
Yrr=5.0 V, Gi=15 pF
Specification value
Observation value
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Output half-transmission delay from low to high
Note: 1) Complete test conditions are listed in Table 3. 2) Only one output terminal is short-circuited
SJ20279—93
Continued Table 1—3
Condition 1
(If not achieved
55 °C≤TA≤125 °C)
Vec=5.0 V, Ce-15 pF
R,-2 kbzxz.net
Table 1-4
Output low voltage
Input voltage
Input cut-off current
Input current at maximum input
Input high current
Input low current
Output high supply current
Output low supply current
Output high to low level transfer delay time Output low to low level transfer delay time
fororF)
Summary: 1) The complete test conditions are listed in Table 3. The electrical characteristics of 54LS15 are shown in Table 1》
(other requirements
55°C≤TAS125\C)
Vcc=4.5 V, lor=4 mA,
Vcc=4.5 V, dk--18 mA
TA-25\C
Vcc-4.5 V, Vu-2.0 V
Ycc=5.5 V, V=7.0 V
Yec=5.5 V, V=2.7 V
Yee=5.5 V, Vi-0.4 V
Ycc=5.5 V,V-4.5 V
Vec=5.5 V, V=-0 V
Vec:=-5.0 V, Gj=15 pF
RL-2k2
Vcc=5.0 V.Gr=15 pF
Normal value
Specification value
Input high level voltage
Input low level current
Input input voltage
Input current
Input low level current
Output current 2)
Output source current when high level
Output source current when low level
Output high to low level transmission delay time Output low to high level transmission delay time SJ 20279—93
Table 1—5 Characteristics of JT54LS21
Item 4:
Note: 1) The complete test conditions are listed in Table 3. 2) Only short-circuit one output terminal at a time. | |tt | Tik--1 ma
TA=25 °℃
Vcs=5.5 V. V,=7.0 V
Vcc=5.5 V, Jf-2.7 V
Ytr-5.5 V. V=0.4 V
Ycc=5.5 V, Vl=4.5 V
Ve=5.s V. V=0 V
Vcc-5.0 V, Gj=15 pF
Ri=2 kn
Vec=5.0 V, CL=15 pF
Rt=2 k
Specification value
The electrical test requirements for the device should be the relevant groups specified in Table 2, and the electrical tests for each group shall be as specified in Table 3. Table 2 Test requirements
Intermediate (before aging) electrical test
Intermediate (after aging) test
Final test
Test requirements for Group A
End point electrical test
Group C: Test requirements for additional electrical tests
Group D: End point electrical test
Class B devices
A2, A3, A9
Classification (see Table 3)
Class B devices
A2.A3. A9
Al. A2, A3, A9, AlU. All
A1, A2, A3
Not required
Note: 1) This group requires PDA calculation (see Section 4.2 of this specification). 10
AI. A2, A3, A9
Al, A2, A3
A10, A11
AE. A2, A3
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