GB/T 3432.4-1989 Semiconductor integrated circuit TTL circuit series and varieties 54/74LS series varieties GB/T3432.4-1989 Standard download decompression password: www.bzxz.net

National Standard of the People's Republic of China
Series and products for 'TL semiconductor integrated circuitsProducts of scries 54/74LS
GB 3432. 4--89
Replaces GB3432-82
This standard specifies the logical functions, external lead arrangements and main electrical parameters of the semiconductor integrated circuit TTL circuit 54/74LS series varieties (hereinafter referred to as the device). The quality assessment of the device shall comply with the provisions of the relevant device detailed specifications. When producing (developing) or selecting devices, their series and varieties shall comply with the provisions of the detailed specifications. Unless otherwise specified, the logic involved in this standard is positive logic. 1 Symbols and codes
1.1 The logical graphic symbols used in this standard comply with GB4728.12 Electrical Diagrams The text symbols used in the standard comply with the provisions of GB3431.1 "Semiconductor Integrated Circuit Text Symbols Electrical Parameters Text Symbols" and GB3431.2 "Semiconductor Integrated Circuit Text Symbols Output Function Symbols". 1.2 The device types and series variety codes listed in this standard are the 0th, 1st and 2nd parts of the device model specified in GB3430 "Semiconductor Integrated Circuit Model Naming Method".
2 Varieties
NAND Gate and Inverter
Six Inverters
Four 2-Input NAND Gate
Four 2 Input NAND Gate (OC)
Three 3-input AND Gate
Dual 4-input NAND Gate
8-input NAND Gate
Six Inverters (OC)
Four 2-input NAND Gate (OC)
Three 3-input NAND Gate (OC)
Dual 4-input NAND Gate (OC)
Six Inverters (with Schmitt Trigger)
Four 2-input NAND Gate (with Schmitt Fuse)Dual 4-input NAND Gate (with Schmitt Fuse)NOR Gate
Four 2-input NOR Gate
Three 3-input NOR Gate
Four 2 Input AND gate
Type and series code approved by the Ministry of Machinery and Electronics Industry of the People's Republic of China on 1989-03-18
CT54LS04/CT74LS04
CT54LS00/CT74LS00
CT54LS01/CT74LS01
CT54LS10/CT74L510
CT541.S20/CT74LS20
CT54LS30/CT74LS30
CT54LS05/CT74LS05
CT54/.S03/CT?4LS03
CT54LS12/CT74LS12
CT54LS22/CT 74LS22
CT54LS14/CT74LS14
CT54LS132/CT74LS132
CT54LS13/CT71LS13
CT54LS02/CT741.S02
CT54LS27/CT741.S27
CT54LS08/CT74LS08
1990-04-01Implementation
Triple 3-input AND Gate
Dual 4-input AND Gate
Quad 2-input AND Gate (OC)
Triple 3-input AND Gate (0℃)
Buffer and Driver
Quad 2-input OR Non-buffer
Quad 2-input AND Non-buffer
Dual 4 Input NAND Buffer
Four 2-input high-voltage output NAND Buffer (OC, 15V)Four 2-input NAND Buffer (OC)
Four 2-input auxiliary input NOR Buffer (OC)
Four bus level buffers (3S)
Four bus buffers (3S.FN high level valid)Six bus drivers (3$, common control)Six inverting bus drivers (3S, common control)Six bus drivers (3S, two groups of control)Six inverting bus drivers (3S, two groups of control)Eight inverting buffers/line drivers/line receivers (3S)Eight buffers/line drivers/line receivers (3S)Eight buffers/line drivers/line transceivers (3S)Eight bidirectional bus transmitters/receivers (3S)OR Gate
Four 2-input OR Gate
AND-OR Gate
2-way 4-4 Input AND-OR gate
4-way 2-3-3-2 input AND-OR gate
2-way 3-3 input, 2-way 2-2 input AND-OR gate trigger and latch
Double falling edge JK trigger (with preset terminal, clear terminal) GB 3432. 4-89
Double falling edge JK trigger (with preset terminal, common clear terminal, common clock terminal) Double falling edge JK trigger (with clear terminal) Double rising edge 3-K trigger (with preset terminal, clear terminal) Double rising edge D trigger (with preset terminal, clear terminal) Eight rising edge D trigger (35, clock input has loopback characteristics) Eight rising edge 1D trigger (Q Terminal output) Six rising edge 1》 flip-flops (Q terminal output, with common clear terminal) Four rising edge D fuses (with common clear terminal) Eight I latches (3S, latch enable input has loopback characteristics) 4-bit 1 latch
. Eight rising edge D flip-flops (Q terminal output, with common eliminate terminal) Four RS registers
8-pull addressable latch
Monostable trigger
Retriggerable monostable trigger (with clear terminal) Dual retriggerable monostable triggers (with clear terminal) Dual monostable triggers (with Schmitt fuse) Arithmetic unit
Dual carry-preserve full adder
Type, series variety code
CT54LS11/CT74LS11
CT54LS21/CT74LS21
CT54LS09/CT74LS 09
CT54LS15/CT74LS15
CT54L$28/CT74LS28
CT54LS37/CT74LS37
CT541.S40/CT74LS40
CT541LS2B/CT74LS26
CT54IS38/CT74L$38
CT54LS33/CT74LS33
CT54LS125/CT74LS125
CT54LS126/CT74LS1 26
CT54LS365/CT74IL.S365
CT54LS366/CT74LS366
CT54LS367/C T74LS367
CT541L.S368/CT74LS368
CT54LS240/CT74LS240
CT54L .S241/CT74LS241
CT$41.S244/CT74LS244
CT54LS245/CT74LS245||tt| |CT54LS32/CT74LS32
CT541.S55/CT74LS55
CT54LS54/CT74L$54
CT54LS51/CT74LS51
CT54LS112/CT74LS112
CT54LS114/CT74LS114||tt ||CT541.S107/CT74LS107
CT541.S109/CT74LS109
CT54LS74/CT74LS74
CT54LS374/CT74LS374
CT54L5377/CT74LS377
CT54L5174/CT74L $174
CT54LS175/CT74LS175
CT54LS373/CT74LS373
CT54L5375/C T74LS375
CT54LS273/CT74LS273
CT541.S279/CT74LS279
Cr541.S259/CT74L8259
CT54LS122/CT741.$122
CT54LS123/CT74LS123
CT54LS221/CT74LS221
CT54LS183/CT74LS183
4-bit arithmetic sequence unit/function generator (32 functions) 2-bit × 4-bit parallel binary multiplier (latch output) 4-bit binary carry-lookahead full adder
7-bit bit slice Wallace tree (3S)
Quad 2-input XOR gate
Quad 2 Input XOR Gate (OC)
4 2-input XOR Gate (OC)
9-bit odd-valve generator/checker
4-bit comparator
Register and shift register
4X4 register array (OC)
4×4 register array (3S)
4-bit shift register (parallel access, small-K input)4-bit associative shift register (35, parallel access)4-bit shift register (parallel access)
B-bit shift register (serial input, parallel output)8-bit shift register (parallel input, complementary parallel output)8-bit shift register (rate, parallel input, parallel output)4-bit bidirectional shift register (parallel access)4-bit D Register (3S, Q output)
8-bit general-purpose shift/storage register (3S, synchronous clear) Clock generator
Voltage controlled oscillator
Priority encoder
10-line-4-line priority encoder (BCD) output) 8-line-3-line priority encoder
8-line-3-line priority encoder (3S)
Data selector
B-select 1 data selector (3S, complementary output) 8-select 1 data selector (with select input, complementary output) 8-select 1 data selector (inverted code output)
Dual 4-select 1 data selector (38)
GB 3432. 4—89
Dual 4-to-1 data selector (with select input, inverted code output)Dual 4-to-1 data selector (3S, inverted code output)Dual 4-to-1 data selector (with select input)4-bit 2-select data selector (register output)Quadruple 2-to-1 data selector (3S, inverted code output)Quadruple 2-to-1 data selector (3S)
Quadruple 2-to-1 data selector (with common select input + code output)Quadruple 2-to-1 data selector (with common select input)Decoder
4-line-10-line decoder (BCD input)
3-line-8-line decoder
Dual 2-line-4-line decoder
Dual 2-line-4-line decoder (with common address input)Dual 2-line-4-line decoder (OC, with common Common address input terminal) 4-line-10-line decoder/driver (BCI) input, (C, can drive lamp. Relay) type, series variety code
GT54LS181/CT74LS181
CT54LS261/CT74LS261
CT54LS283/CT74LS283
CT54L.S275/CT741-S275
CT54 LS8B/CT74LS86
CT54LS136/CT74LS136
CT54LS266/CT74LS266
CT54LS280/C T74LS280
CT54LS85/CT74LS85
CT54LS170/CT74LS170
CT54LS670/CT74LS670
CT54I.S195/CT74LS195
CT541.S395/CT74LS395
CT34L.S95/CT74LS95||tt| |CT54LS164/CT74LS154
CT54LS165/CT74L$165
CT54LS1B6/CT74LS166
CT54L S194/CT74LS194
CF54LS173/CT74L.S173
CT541S323/CT74LS323
CT54L5324 /CT74LS324
CT54LS117/CT74LS147
CT54LS148/CT74LS148
CT54LS348/CT74L .S348
CT54LS251/CT74LS251
CT54LS151/CT74LS151
CT54LS152/CT74LS152| |tt||CT54LS253/CT74LS253
CT541.S352/CT741.S352
CT54LS353/CT74L.S353||tt ||CT54LS153/CT74LS153
C:T54LS298/C1741.S298
CT541.$258/CT74LS238
CT54LS257/CT74L$257
CT54L.S158/CT741.S158
CT54LS157/CT74LS157
CT54 1.S42/CT74LS42
CT541,513B/CT74L$138
CT54L.S139/CT74LS139
CT54L5155/CT741.S155
CT54LS156/CT74LS156
CT541.S145/CT74L.S145
Device Name
GB 3432.4—89
4-wire seven-segment decoder/high-voltage output driver (BCD input, OC.15V)1-wire seven-segment decoder/high-voltage output driver (BCID input OC.15V)4-wire seven-segment decoder/driver (BCD input, with pull-up resistor)4-wire seven-segment decoder/driver (BCD input, with pull-up resistor)4-wire seven-segment decoder/driver (BCD input, OC)4-wire seven-segment decoder/driver (BCD input, OC)Counter
Bi-decimal counter (presettable)
2-digit decimal counter
2-digit hexadecimal counter (presettable)2-digit hexadecimal counter
Dual 4-bit binary counter (asynchronous clear)Decimal synchronous counter (synchronous clear)
Decimal synchronous counter (asynchronous clear)
i-digit step up/down counter
Decimal synchronous up/down counter (dual clock)Up-digit synchronous up/down counter
4-digit binary synchronous counter (same as the division)1-digit binary synchronous counter (asynchronous clear)4 4-bit binary synchronous up/down counter (dual time) 4-bit binary synchronous up/down counter (dual time) 2.1 Six inverters CT54LS04/CT7ALS04 Logic symbol diagram 54-111 54-13 Logic expression Main electrical parameters (typical values) TU = 9.5 ns tt t6) 3y
Logical structure diagram
Type, series and variety code
CT54LS47/CT74LS47
CT54LS247/CT74LS247
CT54L548/CT74LS48
CT54LS246/CT74L$248
CI54LS49/CT74LS49
CT54LS249/CT74I.S249
CT54LS196/CT74LS196
CT34LS290/CT74LS290
CT54LS197/CT741S197
CT54LS203/CT74L $293
CT54LS393/CT74LS393
CT541LS162/CT74LS162
CT54LS16D/CT74LS1G0
CT54LS168/CT741 S168
CT54LS192/CT74LS192
CT54LS190/CT74LS190www.bzxz.net
CT54LS163/CT74LS163
CT54LS161/CT741.S161
CF54LS169/CT74LS109
CT541. S193/CT74LS193
CT541S191/CT74LS191
Pin arrangement diagram
GB 3432.4—89
2.2 Logic symbol diagram of four 2-input NAND gates CT54LS00/CT74LS00
18 —[21
2A-— 14
2 — 15|| tt||381100
Logical expression
YA·B
Main electrical parameters (typical values)
tud = 9. 5ns
Logical structure diagram
P,= 8mW
2.3 Quad 2-input NAND gate (OC)
CT54LS01/CT74LS01
Logic symbol diagram
18 -—( 3)
2A—15)
2B —.6)
3A - t9)
38-[9)
4A131)
48—12)
Logical expression||tt ||YA·B
Logic structure
Main electrical parameters (typical values)
P, = 8mW
Pin arrangement
Pin Arrangement diagram
1+pvec
UND E?
GB 3432. 4—BS
2.4 Logic symbol diagram of three 3-input NAND gate CT54I.S10/CT74LS10
18 —2)
20 15)
38（10
Logical expression
YA·BC
Main electrical parameters (typical values)
tpd = 9. 5ns|| tt||Pr -- GmW
Logic structure diagram
2.5 Dual 4-input NAND gate CT54LS20/CT74LS20 logic symbol diagram
10 - 15)
28( 10F
2c ~(12)
20-13F
Logical expression
Logical structure diagram
YA.BCD
Main circuit Parameters (typical values)
P- 4mw
Pin arrangement diagram
Pin arrangement
2.68 input and NAND gate
GB 3432. 4—89
CT54LS30/CT74LS30|| tt||Logic symbol diagram
Logic expression
Y-AB.CDEFGH
Main electrical parameters (typical values)
fra = 17ns
Pp = 2.4mw
Pin arrangement diagram
Six inverters (OC) CT54LS05/CT74LS05 logic symbol diagram
4A—9
SA111)
6A_131
Logical expression
Main electrical parameters (typical values)
fy = 16ns
tnolsy
Structure diagram
Pg= 12mW
Logic structure diagram
Pin arrangement diagram
14bvre
GB 3432. 4-89
2. 8 Four 2-input NAND gate (OC) CT54LS03/CT74LS03 logic symbol diagram
·4A_{12)
Logic expression
Main electrical parameters (typical values)
td - lGns
t6 ! 2
P. = 8mW
Pin arrangement diagram
2.9 Three 3-input NAND gate (OC) CT54LS12/CT74LS12 logic symbol diagram
TA_(u)
18（21| |tt||1C(13/
2G—15
3B-10)
Logical expression
Main electrical parameters (typical)
tw = 16ns
（121
P= 6mW
Pin arrangement diagram
1ehj3e
2. 10 dual 4-input NAND gate (0C)
CT54LS22ACT74LS22
logic symbol diagram
1B_12]
2A 19)
2日(10）
2C1121
20（135
Logical structure diagram
Logical structure diagram
Pin arrangement diagram
Logical expression| |tt||YA.BC-D
Main electrical parameters: typical value)
f = 16ns
Pu=4mw
GB 3432.4—B9
Logic structure diagram
2.11 Six inverters (with Schmitt trigger) CT5.5:t/CT74LS14 logic symbol diagram
2A -13|| tt||6A_113)
Comply with the logical expression
Main electrical parameters (typical values)
（12)Y
Logical structure diagram
Pin-out terminal Arrangement diagram
tud = 15ns
P= 51.6mw
2.12 Quad 2-input NAND gate (with Schmidt trigger) CT54LS132/CT74LS132 logic symbol diagram
1A--11
18—[2)| |tt||（13)
Logical expression
Y=A·B
Pin arrangement diagram
14bvre
Logical structure diagram|| tt||Main electrical parameters (typical values)
tu = 15ns
I*u = 35. 2m W
GB 3432.4—89
2.13 Dual 4-input NAND gate with Schmitt trigger) CT54LS13/CT74LS13 reverse symbol diagram
18~121
24 191
29 —[19]
2c-112
2D -[13
Logical expression
YA·BC·D
Main electrical parameters (typical Value)
t = 16.5ms
Pp = 17.6mW
Pin arrangement diagram
2.14 Quad 2-input NOR gate CT54LS02/CT71LS021A—[2)
2A — (5
38 - 491
4A—11
Logic symbol diagram
Logic expression
Main electrical parameters (typical values)
tp=10ns
「10]
i4□ vcc
lead terminal arrangement diagram
113h sY
P,=11mW
2.15 three 3 input NOR gate CT541 .S27/CT74LS2?1Am (15
28 41
381101
Logic symbol diagram
Pin arrangement diagram
-3 GNDd
l4 vet
Logic structure diagram
Logic node tree diagram
Logic structure diagram
[A-net
Logic expression
YA-B+C
Main electrical parameter typical values)
tya = 10ns
Pm - 13. 5mw
GB 3432. 4—89
2.16 Logic symbol diagram of four 2-input AND gate CT54LS08/CT74LS08
24—tal
34-191
38（101
4B1131
Remote logic expression
Y=A·B
Main electrical parameters (typical values)
tud = 12ns
Pr =17mW
Pin arrangement diagram
2.17 Logic symbol diagram of three 3-input AND gate CT54L.S1I/CT74LS11
20 161
3A-(9)
381101
Logical expression
Main electrical parameters (typical values)
tw=12k
Pp = 12.75mW
iabveo
Pin arrangement diagram
Logical structure
Logical structure diagram
GB 3432.4—89
2.18 Dual 4-input AND gate CT54LS21/CT741.$211A-[)
18—(2)
28 101
2C1121
2D1131
Logic symbol diagram
Logic expression
YAB·CD
Main electrical parameters (typical values)
tud = 12ns
Pn = 8. 5mW
Pin arrangement diagram
2. 19 Quad 2-input AND gate (OC) CT54LS09/CT74LS09 logic symbol diagram
3A t91
381109
Logic expression
YA·B
Main electrical parameters (typical values)
fut = 20ng
P,= 17mw
Pin-out arrangement
2.20 Three 3-input AND gate (OC) CT54L515/CT74LS151A-11F
18 (2)
10113)
24-13F
Logic symbol diagram
Logic expression
YA·B·C
Main electrical parameters (typical values)
Pin-out arrangement
Logic structure diagram
Logic structure diagram
Logic structure diagram
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