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Ministry of Machinery and Electronics Industry of the People's Republic of China Standard SJ3242---89
Gallium Arsenide Epitaxial Wafer
Issued on March 20, 1989
Implemented on March 25, 1989
Issued by Ministry of Machinery and Electronics Industry of the People's Republic of China
Ministry of Machinery and Electronics Industry of the People's Republic of China Standard Gallium Arsenide Epitaxial Wafer
Subject Content and Scope of Application
SJ3242--89
This standard specifies the brand nomenclature, technical requirements, test methods, inspection rules, marking, packaging, transportation and storage of gallium arsenide vapor phase epitaxial wafers and liquid phase epitaxial wafers. This standard is applicable to the preparation of field effect transistors and varactor diodes. Monumentalized epitaxial wafers for Hall devices and Gunn devices,
2 Reference standards
SJ3244.1 Measurement method for Hall mobility and carrier concentration of indium phosphide and indium phosphide materials SJ3247 Infrared interference test method for thickness of isotype gallium arsenide epitaxial layer SJ3244.4 Measurement method for carrier concentration profile distribution of gallium arsenide and indium phosphide materials - electrochemical voltage capacitance method
SJ3244.3 Measurement method for crystal orientation of indium arsenide and indium phosphide single crystals GB6624
Visual inspection method for surface quality of silicon single crystals GB2828 Batch inspection counting sampling procedure and sampling table (applicable to inspection of continuous batches). 3. Gallium arsenide epitaxial wafer brand naming method
GaAs epitaxial wafer brand naming consists of the following five parts: Four,
The first part is the molecular formula GaAs, which means arsenide. The second part uses the Chinese phonetic letter Q to represent the gas phase, Y to represent the liquid phase, five
The third part uses the Chinese phonetic letter W to represent epitaxy. The fourth part uses Chinese phonetic letters to represent epitaxy for a certain device. CH represents epitaxy for field effect transistors, B represents epitaxy for varactor diodes, G represents epitaxy for Gunn devices, and H represents epitaxy for Hall devices. The fifth part uses Arabic numerals to represent the carrier concentration range. The numerator represents the lower limit, and the denominator represents the upper limit. For example:
GaAsQWCH.5-1016
represents an arsenide vapor phase epitaxial wafer for field effect transistors, with a carrier concentration of 1.5·1017, approved by the Ministry of Machinery and Electronics Industry of the People's Republic of China on March 20, 1989 and implemented on March 25, 1989
SJ3242---89
1016, represents an arsenide liquid phase epitaxial wafer for Hall devices, with a carrier concentration of 5x1016~1.5x1017/cm3, and a GaAsYWH flow concentration of 1015~1016/cm2.
4 Terminology
4.1 Arsenide is a polar semiconductor material. Device and circuit processes require the determination of primary and secondary reference surfaces in order to obtain a specific etching groove shape. The relationship between the reference surface and the etching groove shape is shown in Appendix A. 4.1.1 Main reference plane
Specify the raw reference plane as (OTT) plane, marked with OF, the width of the main reference plane of the wafer depends on the diameter of the single crystal, 4.1.2 Secondary reference plane
Specify the secondary reference plane as (0T1) plane, rotate 90* clockwise along the main reference plane. Marked with IF, the width of the secondary reference plane depends on the diameter of the single crystal.
5 Technical requirements
5.1 The technical specifications of epitaxial wafers used for field effect transistors, varactor diodes, Hall devices and Lian's devices shall meet the requirements of Table 1.
Contact layer
(high power
or
varicap diode
core device
Gun device
active room
buffer layer
contact layer
active layer
buffer layer
active layer
active layer
carrier concentration
(cm-2)
5×101*~1.5× 1017 | | tt | | Pz1x10 | |tt||p1x10t
5×1014~2×101*
1. 0x1171.0x101.
350~450
350~450
350~450
650~450
350~450
Dopant
Gr or 0 or individual
s or si
Cr is 0 or not doped
Si or Te
Cr or 0 or not doped
Sn or s||tt ||Sn or S
Si or Te
Room temperature migration
(em*/VS)
4000~5000
5000~6000
SJ3242-89
5.2 The vertical distribution of carrier concentration of epitaxial wafer for field effect transistor is shown in Figure 1. The transition zone is less than or equal to 1.0μm. Active layer-
5.3 Lateral uniformity of epitaxial wafer
5 .3.1 Measurement location
5.3.1.1 Measurement location of circular wafer
5.3.1.2 Measurement location of rectangular wafer
1 buffer layer
Transition zone
Thickness (μm)
uL point position is on the diagonal line, and is 1/4 of the diagonal length away from the vertex. 5.3.2 Calculation of lateral uniformity of GaAs epitaxial wafer: 5.3.2.1
Carrier concentration
Where: n.||tt| |X100≤10%
SJ3242-89
-u point epitaxial layer carrier concentration, (cm-3), nt-L point epitaxial layer carrier concentration, (cm-3), 5.3.2.1
Epitaxial layer thickness
X10010%
u point epitaxial layer thickness, (μm),
d-L point epitaxial layer thickness, (μm).
Concentration×thickness
nd-n rdt
n..d.+nL.d.
5.4 See Table 3 for dimensions and shape
X100≤10%
Dimensions (mm)
Φ40±1
@50±1
L×B>10×10
L×B≥15×10
5.5 The surface of the epitaxial wafer should be free of pitting, scratches and abrasions. 5.6 The surface of the epitaxial wafer should be smooth and bright, with a roughness of 5.7 The orientation and length of the reference plane are specified in Figure 4 and Table 4. 0.050
Area (cm*)
(2)
(3)
OF (primary reference plane): (01) + 1.
IF (secondary reference plane): (011) ± 5
Figure 4 Position of primary and secondary reference planes
SJ3242—89
Note: If there are special requirements for epitaxial wafers, they should be agreed upon by both the supplier and the buyer. 6 Test methods
6.1 Measurement of carrier concentration and mobility of epitaxial layer 6.1.1 Carrier concentration
The carrier concentration of epitaxial wafers used for Hall devices shall be tested according to SJ3244.1, and the carrier concentration of other epitaxial wafers shall be tested according to SJ3244, 4.
6.1.2 Mobility
The mobility of epitaxial wafers used for field effect transistors and Hall devices shall be tested in accordance with SJ3244.1. For epitaxial wafers used for varactor diodes and Gunn devices, the mobility of the companion wafers shall be measured and tested in accordance with SJ3244.4. 6.2 Measurement of epitaxial layer thickness
The thickness of epitaxial wafers used for Hall devices, Gunn devices, and varactor diodes shall be tested in accordance with SJ3247, or in accordance with Appendix A "Cleavage and Staining Test Method for Epitaxial Layer Thickness". During arbitration, the test shall be conducted in accordance with SJ3247. The thickness of epitaxial wafers used for field effect transistors shall be tested in accordance with SJ3247, or estimated in accordance with GB6618. During arbitration, the test shall be conducted in accordance with SJ3247.
6.3 Crystal orientation measurement
The crystal orientation of the epitaxial wafer is tested according to SJ3244.3. 6.4 The vertical carrier concentration distribution measurement of the epitaxial wafer for field effect transistor is carried out according to SJ3244.1. 6.5 Transverse uniformity measurement
Calculate according to the carrier concentration and epitaxial layer thickness measured in 5.1 and 5.2. 6.6 Dimension measurement
Test with a ruler.
6.7 Surface quality is tested according to GB6624. 6.8 Surface finish measurement
Test according to Appendix C "Infrared Interference Microscope Test Method for Epitaxial Wafer Surface Finish". 6.9 Reference plane orientation and length measurement
Test according to the method agreed upon by both parties. 7 Inspection rules
7.1 An inspection batch consists of epitaxial wafers of the same nominal size and the same characteristics. The inspection batch of epitaxial wafers is normally inspected according to GB2828 and a single sampling plan is carried out.
7.2 Inspection items
All inspection items for epitaxial wafers are shown in Table 5. When otherwise specified in the order contract, it shall be handled in accordance with the order contract. 5
Inspection group
Inspection items
Electrical properties
Lateral uniformity
Dimensions
Surface quality
SJ324289
Inspection requirements
41Table 1
4.1Table 1
4.1Table 1
Field effect transistor longitudinal carrier concentration distribution Smoothness
Reference surface
4,2
Inspection level
Qualified quality level
Agreement between supply and demand parties
Agreement between supply and tape parties
Note: For Group F, if the surface failure is caused by contamination, it is allowed to clean all the products submitted for inspection and re-inspect. 7.3 Determination of inspection results
The inspection batches that have all passed the inspection of groups 4, B, C, D, E, F, G, H, and I in Table 5 are qualified batches. If any group fails the inspection, the inspection batch is judged to have failed the initial inspection. 7.4 Re-inspection rules
For inspection batches that have failed the initial inspection, re-inspection is allowed after all the products of the inspection batch are returned for repair and it is proved that the original defects have been overcome. The batch submitted for re-inspection should be composed of products in the original inspection batch. The inspection group that originally failed should be re-inspected. If the performance of a certain inspection group may be affected during repair, the inspection group should also be re-inspected. The re-inspection adopts a stricter inspection sampling plan. Inspection batches that fail the re-inspection are judged to be unqualified products. 7.5 When the purchaser receives the product, he shall promptly unpack it according to the product delivery note and check whether the product is complete. If the product is damaged due to poor packaging quality or if the product quality is found to be inconsistent with the product certificate, he shall report it to the supplier within one month from the date of arrival according to the original batch number, and the supply and demand parties shall negotiate to resolve it. 8 Packaging, marking, transportation and storage
8.1 After the epitaxial wafer passes the inspection, it shall be placed in a special polyethylene plastic box. Several small boxes (from the same batch) shall be placed in a plastic box together with the quality certificate. Several plastic boxes shall be placed in a wooden box, and the box shall be filled with soft fillers so that the plastic box will not move inside the box.
8.2 Marking
8.2.1 The wooden box should have the following markings
1) Manufacturer's name
2) Product name, brand, number:
3) Number of boxes
4) Contract number:
5) Date of manufacture;
6) Shockproof: moisture-proof mark.
SJ3242—89
8.2.2 Each batch of products should be accompanied by a quality certificate, which should indicate: 1) Manufacturer's name;
2) Product name, brand, batch number;
3) Various technical performance indicators specified in the contract; 4) Number of pieces;
5) Signature and inspection date of the inspector (or inspection department). 8.3 Products should not be mixed, transported or stored with corrosive substances such as acids and alkalis during transportation and storage. 8.4 The product should be stored in a dry and clean warehouse. 7
SJ3242-89
Appendix A
Schematic diagram of the relationship between the reference surface and the shape of the corrosion groove (reference)
V-shaped phase
IF (secondary reference surface)
/(100)
inoni)
Swallowtail
OF (primary reference surface)
SJ3242-89
Appendix B
Test method for cleavage staining of epitaxial layer thickness (supplementary)
This method is applicable to the determination of the thickness of the GaO epitaxial layer. B1 Test principle
Use the characteristics that the chemical etching rate changes with the semiconductor carrier concentration and the etching rate is fast at the boundary between the substrate and the epitaxial layer. The boundary between the substrate and the epitaxial layer of the product wafer is displayed by chemical etching. B2 Instruments and reagents
B2.1 Instruments
Metallographic microscope.
B2.2 Etching solution formula
Kg (Fe (CN) 6) KOH: HzO 10g: 10g: 100mlB3 Test steps
Press the edge of the back of the epitaxial wafer with a blade, and the wafer will be cleaved along the <110> plane. Take the fragments and etch them at room temperature to make the boundary between the substrate and the epitaxial layer clearly visible. Use a 300-500 times metallographic microscope to directly observe the thickness of the epitaxial layer. For the epitaxial layer of the low-resistance substrate, it takes about 30 seconds to etch, and for the epitaxial layer of the medium-resistance or high-resistance substrate, it takes about 60-90 seconds to etch.
B4 Test report
The test report should include the following contents:
a, sample source,
b, measurement date;
epitaxial layer thickness,
SJ3242--89
Appendix C
Infrared interference microscope test method for epitaxial wafer surface finish (supplement)
This method is applicable to the detection of surface finish of GaN epitaxial wafer. G1
Test principle
Using the coherence phenomenon of light, a light source is decomposed into two corresponding waveguides. The superposition of the two waveguides can observe interference fringes on the microscope, and the interference optical path difference can be obtained. C2 Instrument
Infrared interference microscope
C3 Test steps
C3.1 Use propylene glycol and anhydrous ethanol to remove the oil stains on the surface of the epitaxial wafer, and then rinse and dry with deionized water. C3.2 Place the sample on the sample holder and adjust the distance of the microscope lens to make the interference fringes clearly visible; C3.3 Read the fringe curvature and the interference fringes spacing. C4 Measurement results
C4.1. Calculate
Interference fringe path difference A=nλ/2
Where: n—ratio of fringe curvature to interference fringe spacing; λ—interference light wavelength um.
2 The corresponding relationship between interference fringe path difference and roughness is shown in Table 6 Table 6
Interference fringe path difference
Roughness
5 Test report
The test report should include the following contents
Sample source:
Measurement date;
c. The degree of clarity.
Additional Notes:
About the corresponding table of fringe path difference and roughness
0.12~0.25
This standard was drafted by the 46th Institute of the Ministry of Machinery and Electronics Industry0.06~0.12
Main drafters of this standard: Ru Qiongna, Li Guangping, He Xiukun, Wang Qin, Xie Chongmu105 When the purchaser receives the product, he shall promptly unpack it according to the product delivery note and check whether the product is complete. If the product is damaged due to poor packaging quality or if the product quality is found to be inconsistent with the product certificate, he shall report it to the supplier within one month from the date of arrival according to the original batch number, and the supply and demand parties shall negotiate to resolve it. 8 Packaging, marking, transportation and storage
8.1 After the epitaxial wafer passes the inspection, it shall be placed in a special polyethylene plastic box. Several small boxes (from the same batch) shall be placed in a plastic box together with the quality certificate. Several plastic boxes shall be placed in a wooden box, and the box shall be filled with soft fillers so that the plastic box will not move inside the box.
8.2 Marking
8.2.1 The wooden box should have the following markings
1) Manufacturer's name
2) Product name, brand, number:
3) Number of boxes
4) Contract number:
5) Date of manufacture;
6) Shockproof: moisture-proof mark.
SJ3242—89
8.2.2 Each batch of products should be accompanied by a quality certificate, which should indicate: 1) Manufacturer's name;
2) Product name, brand, batch number;
3) Various technical performance indicators specified in the contract; 4) Number of pieces;
5) Signature and inspection date of the inspector (or inspection department). 8.3 Products should not be mixed, transported or stored with corrosive substances such as acids and alkalis during transportation and storage. 8.4 The product should be stored in a dry and clean warehouse. 7
SJ3242-89
Appendix A
Schematic diagram of the relationship between the reference surface and the shape of the corrosion groove (reference)
V-shaped phase
IF (secondary reference surface)
/(100)
inoni)
Swallowtail
OF (primary reference surface)
SJ3242-89
Appendix B
Test method for cleavage staining of epitaxial layer thickness (supplementary)
This method is applicable to the determination of the thickness of the GaO epitaxial layer. B1 Test principle
Use the characteristics that the chemical etching rate changes with the semiconductor carrier concentration and the etching rate is fast at the boundary between the substrate and the epitaxial layer. The boundary between the substrate and the epitaxial layer of the product wafer is displayed by chemical etching. B2 Instruments and reagents
B2.1 Instruments
Metallographic microscope.
B2.2 Etching solution formula
Kg (Fe (CN) 6) KOH: HzO 10g: 10g: 100mlB3 Test steps
Press the edge of the back of the epitaxial wafer with a blade, and the wafer will be cleaved along the <110> plane. Take the fragments and etch them at room temperature to make the boundary between the substrate and the epitaxial layer clearly visible. Use a 300-500 times metallographic microscope to directly observe the thickness of the epitaxial layer. For the epitaxial layer of the low-resistance substrate, it takes about 30 seconds to etch, and for the epitaxial layer of the medium-resistance or high-resistance substrate, it takes about 60-90 seconds to etch.
B4 Test report
The test report should include the following contents:
a, sample source,
b, measurement date;
epitaxial layer thickness,
SJ3242--89
Appendix C
Infrared interference microscope test method for epitaxial wafer surface finish (supplement)
This method is applicable to the detection of surface finish of GaN epitaxial wafer. G1
Test principle
Using the coherence phenomenon of light, a light source is decomposed into two corresponding waveguides. The superposition of the two waveguides can observe interference fringes on the microscope, and the interference optical path difference can be obtained. C2 Instrument
Infrared interference microscope
C3 Test steps
C3.1 Use propylene glycol and anhydrous ethanol to remove the oil stains on the surface of the epitaxial wafer, and then rinse and dry with deionized water. C3.2 Place the sample on the sample holder and adjust the distance of the microscope lens to make the interference fringes clearly visible; C3.3 Read the fringe curvature and the interference fringes spacing. C4 Measurement results
C4.1. Calculate
Interference fringe path difference A=nλ/2
Where: n—ratio of fringe curvature to interference fringe spacing; λ—interference light wavelength um.
2 The corresponding relationship between interference fringe path difference and roughness is shown in Table 6 Table 6
Interference fringe path difference
Roughness
5 Test report
The test report should include the following contents
Sample source:
Measurement date;
c. The degree of clarity.
Additional Notes:
About the corresponding table of fringe path difference and roughness
0.12~0.25
This standard was drafted by the 46th Institute of the Ministry of Machinery and Electronics Industry0.06~0.12
Main drafters of this standard: Ru Qiongna, Li Guangping, He Xiukun, Wang Qin, Xie Chongmu105 When the purchaser receives the product, he shall promptly unpack it according to the product delivery note and check whether the product is complete. If the product is damaged due to poor packaging quality or if the product quality is found to be inconsistent with the product certificate, he shall report it to the supplier within one month from the date of arrival according to the original batch number, and the supply and demand parties shall negotiate to resolve it. 8 Packaging, marking, transportation and storage
8.1 After the epitaxial wafer passes the inspection, it shall be placed in a special polyethylene plastic box. Several small boxes (from the same batch) shall be placed in a plastic box together with the quality certificate. Several plastic boxes shall be placed in a wooden box, and the box shall be filled with soft fillers so that the plastic box will not move inside the box.
8.2 Marking
8.2.1 The wooden box should have the following markings
1) Manufacturer's name
2) Product name, brand, number:
3) Number of boxes
4) Contract number:
5) Date of manufacture;
6) Shockproof: moisture-proof mark.
SJ3242—89
8.2.2 Each batch of products should be accompanied by a quality certificate, which should indicate: 1) Manufacturer's name;
2) Product name, brand, batch number;
3) Various technical performance indicators specified in the contract; 4) Number of pieces;
5) Signature and inspection date of the inspector (or inspection department). 8.3 Products should not be mixed, transported or stored with corrosive substances such as acids and alkalis during transportation and storage. 8.4 The product should be stored in a dry and clean warehouse. 7
SJ3242-89
Appendix A
Schematic diagram of the relationship between the reference surface and the shape of the corrosion groove (reference)
V-shaped phase
IF (secondary reference surface)
/(100)
inoni)
Swallowtail
OF (primary reference surface)
SJ3242-89
Appendix B
Test method for cleavage staining of epitaxial layer thickness (supplementary)
This method is applicable to the determination of the thickness of the GaO epitaxial layer. B1 Test principle
Use the characteristics that the chemical etching rate changes with the semiconductor carrier concentration and the etching rate is fast at the boundary between the substrate and the epitaxial layer. The boundary between the substrate and the epitaxial layer of the product wafer is displayed by chemical etching. B2 Instruments and reagents
B2.1 Instruments
Metallographic microscope.
B2.2 Etching solution formula
Kg (Fe (CN) 6) KOH: HzO 10g: 10g: 100mlB3 Test steps
Press the edge of the back of the epitaxial wafer with a blade, and the wafer will be cleaved along the <110> plane. Take the fragments and etch them at room temperature to make the boundary between the substrate and the epitaxial layer clearly visible. Use a 300-500 times metallographic microscope to directly observe the thickness of the epitaxial layer. For the epitaxial layer of the low-resistance substrate, it takes about 30 seconds to etch, and for the epitaxial layer of the medium-resistance or high-resistance substrate, it takes about 60-90 seconds to etch.
B4 Test report
The test report should include the following contents:
a, sample source,
b, measurement date;
epitaxial layer thickness,
SJ3242--89
Appendix C
Infrared interference microscope test method for epitaxial wafer surface finish (supplement)
This method is applicable to the detection of surface finish of GaN epitaxial wafer. G1
Test principle
Using the coherence phenomenon of light, a light source is decomposed into two corresponding waveguides. The superposition of the two waveguides can observe interference fringes on the microscope, and the interference optical path difference can be obtained. C2 Instrument
Infrared interference microscope
C3 Test steps
C3.1 Use propylene glycol and anhydrous ethanol to remove the oil stains on the surface of the epitaxial wafer, and then rinse and dry with deionized water. C3.2 Place the sample on the sample holder and adjust the distance of the microscope lens to make the interference fringes clearly visible; C3.3 Read the fringe curvature and the interference fringes spacing. C4 Measurement results
C4.1. Calculate
Interference fringe path difference A=nλ/2
Where: n—ratio of fringe curvature to interference fringe spacing; λ—interference light wavelength um.
2 The corresponding relationship between interference fringe path difference and roughness is shown in Table 6 Table 6
Interference fringe path difference
Roughness
5 Test report
The test report should include the following contents
Sample source:
Measurement date;
c. The degree of clarity.
Additional Notes:
About the corresponding table of fringe path difference and roughness
0.12~0.25
This standard was drafted by the 46th Institute of the Ministry of Machinery and Electronics Industry0.06~0.12
Main drafters of this standard: Ru Qiongna, Li Guangping, He Xiukun, Wang Qin, Xie Chongmu10Calculation
Interference fringe path difference A=nλ/2
Where: n—ratio of fringe bending height to interference fringe spacing; λ—interference light wavelength um.
2The corresponding relationship between interference fringe path difference and roughness is shown in Table 6Table 6
Interference fringe path difference
Roughness
5Test report
The test report should include the following contents
Sample source:
Measurement date;
c. Optical clarity level.
Additional instructions:
About the corresponding table of interference fringe path difference and roughnessWww.bzxZ.net
0.12~0.25
This standard was drafted by the 46th Institute of the Ministry of Machinery and Electronics Industry0.06~0.12
Main drafters of this standard: Ru Qiongna, Li Guangping, He Xiukun, Wang Qin, Xie Chongmu10Calculation
Interference fringe path difference A=nλ/2
Where: n—ratio of fringe bending height to interference fringe spacing; λ—interference light wavelength um.
2The corresponding relationship between interference fringe path difference and roughness is shown in Table 6Table 6
Interference fringe path difference
Roughness
5Test report
The test report should include the following contents
Sample source:
Measurement date;
c. Optical clarity level.
Additional instructions:
About the corresponding table of interference fringe path difference and roughness
0.12~0.25
This standard was drafted by the 46th Institute of the Ministry of Machinery and Electronics Industry0.06~0.12
Main drafters of this standard: Ru Qiongna, Li Guangping, He Xiukun, Wang Qin, Xie Chongmu10
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