This standard applies to the development, production and procurement of devices. SJ 20157-1992 Semiconductor Integrated Circuit JT54LS32 and JT54LS86 LS-TTL OR Gate Detailed Specification SJ20157-1992 Standard download decompression password: www.bzxz.net

SJ20157---92 Military Standard of the Electronic Industry of the People's Republic of China Detail specification for types JT54LS32 and JT54LS86 OR GATES of LS-TTL semiconductor integrated circuits circuits1992-11-19 Issued
1993-05-01 Issued by the Ministry of Machinery and Electronics Industry of the People's Republic of China 1 Category
Subject Content
1.2 Applicable Use
1.3 Classification
2 Referenced Documents
3 Requirements
3.1 Detailed Requirements
3.2 Design, Structure and Dimensions
Lead Materials and Coating
Electrical Characteristics
Electrical Test Requirements
Division of Microcircuit Groups
Quality Assurance Provisions
Sampling and Inspection
Identification and inspection
4.4 Quality--Conformity inspection
Inspection method
5 Delivery preparation
5.1 Packaging requirements
6 Notes
6.1 Intended use
6.2 Ordering information
6.3 Abbreviations, symbols and definitions
6.4 Substitution
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People's Republic of China Electronic Industry Military Standard Semiconductor Integrated Circuits
5SJ20157-92
Detailed specification for LS-TTL OR gates of type JT54LS32 and JT54LS86 specification for types JT54LS32 and JT54LS86 OR GATESof LS-TL semiconductor integrated circuits 1 Scope
1.1 Subject matter
This specification specifies the detailed requirements for semiconductor integrated circuits JT54LS32 and JT54LS86 types LS---TTL OR gates (hereinafter referred to as devices).
1.2 Scope of application
This specification applies to the development, production and procurement of devices. 1.3 Classification
The devices given in this specification are classified according to device model, device grade, package form, rated value and recommended operating conditions.
1.3.1 Device numbering
The device numbering shall be in accordance with the provisions of Article 3.6.2 of GJB597 "General Specification for Microcircuits". 1.3.1.1 Device model
The device model is as follows:
JT54LS32
JT54LS86
1.3.1.2 Device grade
Device name
Quad 2-input gate
Quad 2-input XOR gate
The device grade is B grade specified in Article 3.4 of GJIB597 and BI grade specified in this specification. 1. 3. 1. 3 Package form
The package form is as follows:
Approved by the Ministry of Machinery and Electronics Industry of the People’s Republic of China on November 19, 1992 and implemented on May 1, 1993
Absolute maximum ratings
The absolute maximum ratings are as follows
Power supply voltage
Input voltage
Storage temperature
Power 1)
Lead soldering heat (10s)
SJ 20157—92
Packaging form (according to GB7092 "Semiconductor integrated circuit dimensions") C20P3 (ceramic leadless chip carrier package) D14S3 (ceramic dual-in-line package)
F14X2 (ceramic fan-type flat package)
H14X2 (ceramic olefin-sealed flat package)
J14S3 (ceramic fusion-sealed dual-in-line package)
Note: 1) The device should be able to withstand the increased power consumption when the output short-circuit current (or) is tested. 1.3.3 Operating conditions
The recommended operating conditions are as follows:
Output source voltage
Input high level voltage
Input low level voltage
Input high level current
Input low level current
Operating environment
Referenced documents
GB3431.1—82 Semiconductor integrated circuit symbol Electrical parameter symbol Semiconductor integrated circuit symbol Terminal function symbol GB 3431.2—86
GB3439-82 Basic principles of semiconductor integrated circuit TTL circuit test methods GB4590·84 Mechanical and climatic test methods for semiconductor integrated circuits GB4728.12—83 Graphic symbols for electrical diagrams Binary logic unit GB 709293
GJB 548--88
GIB 597—88
Dimensions of semiconductor integrated circuits
Test methods and procedures for microelectronic devices
General specification for microcircuits
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SJ20157—92
GJBZ105 Manual for the control of electrostatic discharge of electronic products 3 Requirements
3.1 Requirements
All requirements shall be in accordance with the provisions of GIB597 and this specification. 3.2 Design, structure and dimensions
Design, structure and appearance The size shall comply with the provisions of GJB597 and this specification. 3.2.1 Logic symbols, logic diagrams and pin arrangement The logic symbols, logic diagrams and pin arrangement shall comply with the provisions of Figure 1. The pin arrangement is a top view. Symbol
Diagram
JT54LS32
JT54LS86
Pin arrangement
D, F, H, J type
3.2.2 Function table
The function table is as follows:
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Figure 1 Logic symbol, logic diagram Li Hongshan terminal arrangement output
JT54LS32
3.2.3 Power supply schematic
JT54LS86
The manufacturer shall submit the electrical schematic to the appraisal agency before appraisal. The electrical schematic shall be filed with the appraisal agency for future reference. 3.2.4 Packaging form
The packaging form shall comply with the provisions of Article 1.3.1.3 of this specification. 3.3 Lead material and coating
The lead material and coating shall comply with G JB597 Article 3.5.6. 3.4 Electrical Characteristics
The characteristics shall comply with the provisions of Table 1.
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Build the heart and wait in the middle!
Input clamp also Chuan
Maximum input also left input also current
Input high ratio current
Input low level current
Output circuit 23
High level power supply current
Low level power supply current
Transmission delay time
SJ 26157—92
Table 1—1Electrical characteristics of JT54LS32
Conditions)
Note: 1) The complete test conditions are listed in Table 3. 2) Only one yoke terminal can be tested at a time
No other conditions are
-55 °C≤T≤125 °C
Ycc=4.5 V, ViH-2.0 V
Io--400μA
Vcc=4.5 V, Vrh-2.0 V
ViL=0.7 V, foL=4 mA
Vec=4.5 V, Inx--18 mA
T-25 °℃
Vece-5.5 V. Vi-7.0 V
Vec=5.5 V, V,-2.7 V
Yer=5.5 V, V-0.4 V
Vcc=5.5 V
Ycc=5.5 V, V=4.5 V
Vcc=5.5 V. V=0 V
Vec=5.0 V, Rt-2 ks2.
CL=15 pF
Table 1-2 Electrical characteristics of JT54LS86
Bar 1
Input high level current
Output voltage
Input low voltage
Input current at large input voltage
Input voltage drop
Input short circuit current
Power supply current
Unless otherwise specified
-55 °C≤T≤125 °C
Vcc=4.5 V, Vif-2.0 V
LO-400μA
Vcc=4.5 V, Vih-2.0 V
VIL-0.7 V, for=4 mA
Vcc-4.5 V, lk--18 mA
TA=25PC
Vcr=5.5 V, V-7.0 V
Vec5.5 V, V-2.7 V
Vor-5.5 V, Pj-0.4 V
Vox=5.5 V
Vec=5.s V
Specification
Specification valuebzxZ.net
Transmission delay time
Note: 1) Complete test conditions are listed in Table 3 2) Only one output terminal can be short-circuited at a time:
3.5 Electrical test requirements
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Continued Table 1-2
Condition 1
If not otherwise specified
55 °C≤T ≤125 °℃
Vcc=5.0V,
Rr=2ko2,
Gt=15pF
A, B→Y
(non-tested input
is low level)
A, BY
(non-source input
is high level)
Specification setting
The electrical test requirements for all-level devices should be the relevant divisions specified in Table 2. The electrical tests for each group shall be as specified in Table 3. Table 2 Electrical test requirements
Intermediate (before aging) electrical test
Intermediate (after aging) electrical test
Final electrical test
A follow-up test requirements
Group C end-point heart test
Group C inspection added group
Group D end-point electrical test (Method 5005)
Class B devices
A2, A3, A9
Paper separation (see Table 3)
Class B1 devices
A2. A3,A9
Al,A2，A3,A9,A10,A11
At. A2, A3
Not required
Al,A2,A3
Note: 1) This subsection requires PDA calculation (double 4.2). 6
AI,A2,A3, A9
A1. A2、 A3
A10,A1l
Al,A2、A3
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Reference standard
GB 3439
SJ 20157—92
Table 3—1JI54LS32 Group A electrical test
Yce=4.5V, input V-2.0 at one end of the gate being tested V, and any other input, all other inputs are -4.5V, the measured output Jo--400μA
Vcc=4.5V, all inputs of the measured gate VIL=0.7V, all other inputs V-4.5 V, the measured output loL =4 mAVcc=4.5 V, the measured gate input Iik=-18 mAVcc:=5.5 V, the measured} end input V=7.U VH all other inputs Y=0 V
Vcc=5.5 V, the measured gate input V2.7 V, all other inputs V=0 V
Vec =5.5 V, the measured gate-end input Yi=0.4 V, all other inputs V=4.5V
Vec-5.5V, all inputs of the gate under test V,=4.5V, all other inputs open circuit
Vcc=5.5V, all inputs of the gate under test Y-4.5 VVcc-5.5V, all inputs of the gate under test V=0VSpecification value
TA=125°C, except Vik is not tested, the parameters, conditions, and specification values ​​are required to be grouped with AI. Except IA--55°C, except Yk is not tested, the parameters, conditions, and specification values ​​are required to be grouped with A1. tpHI.
Vcc=5.0V, see
A, B-→Y in this specification diagram 2
Except T--55 °C, parameters, conditions and specification values ​​are the same as group A10, the most popular
referenced standards
GB3439
SJ 20157--92
Table 3~2JT54LSB6 group A electrical test
Vcc=4.5 V, the gates under test are input with ViL=0.7V and Vm=2.0 V respectively, all other inputs are Vt=4.5 V, and the output IoH =-400 μA
Vcc:=4.5V, the gate under test inputs Vm-2.0V (or Vn=0.7V) respectively, all other inputs H=4.5V, the output under test JoL=4 mA
Ycc+4.5 V, one end of the gate under test inputs /k*-1B mAVcc-5.5V, the - end of the gate under test inputs V=7.0V, all other inputs;= V
Vce=5.5V The - end of the gate under test inputs V=2.7V, all other inputs Y-0 V
Vcc=5.5V, one end of the gate under test inputs V=0.4 V, H, all other inputs Y=4.5V
Vcc=5.5V, all inputs V=0V, all other inputs open
Yc=5.5V, all inputs V,=0V
T=125℃, except V is not tested, the parameters, conditions, and specification values ​​are the same as those in A1 group. Specification values
Except TA=-55℃, except VIx is not tested, the parameters, conditions, and specification values ​​are the same as those in A1 group. fpir
Vec=5.0V, this specification figure
TA-125°℃,
see figure 2 of this specification
A, B-→Y
(non-tested input is low
electric rate)
A, B-→Y
(non-tested input is high
heart level)
A, B-→Y
(non-tested input is low
(non-tested input is high
A11Except TA=-55°C, the parameters, conditions, and specification values ​​are grouped with A10.-8
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Load line
Test point Yce
SJ 20157—92
Real level
+-telt
JT54LS32
JT54LS86
Note: (Input waveform: f-1MHz, t≤15ns, t6 ns, ts0.5μus. ②R,=2k±5%, CL=15pF±10% (including head and fixture capacitance), diode is 2CK76 or its equivalent model. Figure 2 Load circuit and 1 waveform
3.6 Marking
The marking shall be in accordance with the provisions of Article 3.6 of GJB597
Division of microcircuit groups
The devices involved in this specification are the 8th microcircuit group (see Appendix F of GJB597). 4 Quality assurance regulations
4.1 Batch sample inspection
Except as otherwise specified in this specification, the sampling and inspection procedures shall be in accordance with the provisions of GJBS97 and GJB548 Method 5005. 4.2 Screening
Before identification and quality conformity inspection, all devices should be screened according to GJB548 Method 5004 and Table 4 of this specification.
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Table 4 Screening Procedure
If there is no other provision, the method used in the table refers to the test method of GJB548. Methods and conditions
Internal H stability
(before capping;
Stability roasting (tea
end point test required)
Overflow cycle
Constant acceleration
South (before polymerization)
Electrical test
Intermediate (aging data)
Class B devices
2010|Test condition B
Test condition C (150
Test condition C
Test condition L, YI
direction.
This specification A1 group
Test conditions: D(125
oC,1G0h)
This specification A1 dividend
Allowed defective product 5%, this specification A1 group, pull (PDA) calculation| |tt||Final test
Detailed leak test
External daily inspection
If the defective product rate does not exceed
10%, it can be resubmitted for aging,
but only once.
This specification A2, A3,
A9 dimension
identification or quality conformity'5005
quality inspection Test sample for inspection
4.3 Qualification inspection
Article 3.5
R1 grade
! Test condition B
Test condition C (150
c℃, 24h)
Test condition C
Test condition D, YI
Square,
This specification A1 group
1015 ！ Test conditions [（125
aC, 160h)
This specification A1 group
10%, this specification AI group, when
the defective rate does not exceed 20%, the pot is submitted for aging, and only one charge is allowed.
This specification A2, A3,
A9 group
Article 3.5
The applicable method is 1011 Test conditions A is replaced. It is called after the "open seal" screening. Broken leads, cracked shells, and falling covers are considered failures. The manufacturer decides whether to conduct this screening. The circuit in Figure 3 of this specification is used. All batches. If the intermediate electrical test is not performed before aging, the effectiveness of the intermediate (after aging) electrical test A1 correction should also be included. After this screening, if the lead coating is changed or reworked, the A1 group test should be performed again. The identification inspection should be in accordance with the provisions of GJB597, and the physical inspection should comply with GJB548 Method 5005 and this specification A, - 10
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