GB/T 11324-1995 139264 kbit/s positive code rate adjustment four-group digital multiplexing equipment technical requirements and test methods
Some standard content:
UDC621.394.6
National Standard of the People's Republic of China
GB/T11324—1995
139264kbit/s positive justification
Technical requirements and test methods of the fourth orderdigital multiplex equimpent operating at139264kbit/sandusingpositivejustification1995-04-06Promulgated
State Administration of Technical Supervision
1995-12-01Implementation
National Standard of the People's Republic of China
139264kbit/s positive justification
Technical requirements and test methods of the fourth orderdigital multiplex equimpent operating This standard is equivalent to the CCITTG.751 recommendation. 1 Subject content and scope of application
GB/T11324-1995
Replaces GB11324~11325-89
This standard specifies the technical requirements and test methods for four-group digital multiplexing equipment using positive code rate adjustment at 139264 kbit/s. This standard applies to four-group digital multiplexing equipment using positive code rate adjustment at 139264 kbit/s used in digital transmission systems.
2 Reference standards
Pulse code modulation communication system series
GB4110
Pulse code modulation communication system network digital interface parameters GB7611
3 Working conditions
3.1 Environmental conditions for use
Temperature: 5~40℃,
Relative humidity: ≤85% (30℃);
Atmospheric pressure: 70~106kPa.
3.2 Power supply
Power supply voltage: -48V±20%.
4 Basic parameters
4.1 Bit rate
The nominal bit rate of the multiplexed signal is: 139264 kbit/s, with a tolerance of ±15×16-6. The nominal bit rate of the branch signal is: 34368 kbit/s, with a tolerance of ±20X10-6. 4.2 Frame structure
The frame structure of this multiplexer is listed in Table 1.
Approved by the State Bureau of Technical Supervision on April 6, 1995 and implemented on December 1, 1995
Branch bit rate, kbit/s
Number of branches
Frame structure
Frame positioning signal (111110100000)
Alarm indication to the digital multiplexing equipment at the other end Bits reserved for domestic use
Bits from each branch
GB/T11324—1995
Table 1139264 kbit/s multiplexing frame structure
Comparison Special number
17~488
Group 1~v
Rate adjustment service bits C, (n=1~4) Note) Bits from each branch
Rate adjustment service bits Cis (Note)
Bits from each branch that can be used for rate adjustment Bits from each branch
Frame length, bit
Number of bits per branch, bit
Maximum rate adjustment rate per branch, kbit/s Nominal rate adjustment ratio
Note: C represents the nth rate adjustment control bit of the 3rd branch. 4.3 Frame loss and frame alignment recovery
4.3.1 When erroneous frame alignment signals are received at their predetermined positions for four consecutive frames, it is considered that frame loss has occurred. 4.3.2 After a frame loss, when frame alignment signals are detected for three consecutive frames, it should be judged that frame alignment has been effectively restored. If after the frame alignment signal is detected, but one of the two frames after it is not detected, the search for the alignment signal should be repeated.
4.4 Multiplexing method
4.4.1 Multiplexing method
Multiplex bit by bit in a cyclic manner in the order of branch numbers. 4.4.2 Code rate adjustment method
Positive code rate adjustment, inserted at a fixed position. wwW.bzxz.Net
4.4.3 Code rate adjustment control signal
5 bits per branch, should be distributed and use C (n=1, 2, 3, 4, 5). The signal "11111" is used to indicate code rate adjustment, and the signal "00000" is used to indicate no code rate adjustment, and detection is performed using the majority decision method. 4.4.4 Code rate adjustment bit
1 bit per branch, fixed immediately after the code rate adjustment bit C. When there is a code rate adjustment, it is the adjustment bit and no information is transmitted. When there is no code rate adjustment, it is the branch bit and information is still transmitted. 4.5 Official digital
Four bits in each frame can be used for official business. When a specific fault is detected in the multiplexing equipment, bit 13 of group I is used to send an alarm indication to the multiplexing equipment at the other end (see 5.4.2.2). Bits 14 to 16 of group I are reserved for domestic use (the method of use is to be determined). On digital channels across national borders, this bit is fixed to "1". 5 Technical requirements
5.1 Digital interface
5.1.134368kbit/s interface
5.1.1.1 Nominal bit rate: 34368kbit/s; tolerance: ±20×10-6;
Code type: HDB3.
GB/T11324—1995
2 Overvoltage protection requirements: see Appendix A (supplement). 5. 1.1.2
5.1.1.3 34368 kbit/s output port requirements: see Table 2 and Figure 1. Table 234368kbit/s output port general requirements pulse shape: Nominal pulse shape is rectangular Line pair in each transmission direction
Test load impedance
Nominal peak voltage of pulse (signal)
Peak voltage of no pulse (space)
Nominal pulse width
Positive and negative pulse amplitude ratio at the midpoint of pulse width
Positive and negative pulse width ratio at half amplitude of pulse
Regardless of polarity, all valid signal pulses (signals) should meet the limits of the template given in Figure 1
Coaxial line pairs
752Resistance
0.95~1.05
0.95~1.05
(1:. 65+ 0. 3F)
c1.1. a. + I+. 530
Figure 134368kbit/s interface pulse mode frame
5.1.1.434368kbit/s input port requirements5.1.1.4.1 Input impedance
Nominal value: 752 (coaxial),
Input impedance characteristics: see Table 3.
Frequency range, kHz
860~1720
1720~34368
34368~51550
5.1.1.4.2 Permissible attenuation at the input port
GB/T11324—1995
Table 334368 kbit/s input port impedance characteristics return loss, dB
The digital signal appearing at the input port shall be as specified in Table 2, but it is allowed to vary depending on the transmission line pairs used to connect the output port and the input port, and the input port shall be able to adapt to these variations. The attenuation frequency characteristics of these line pairs shall approximately conform to the √ law, and the minimum change in the attenuation value at the frequency point of 17184 kHz shall reach 0~12 dB. This attenuation value shall include any attenuation introduced by the digital patch panel between the output port and the input port. 34368kbit/s port maximum allowable input jitter tolerance: see Table 4 and Figure 2. 5. 1.1.4.3
Table 4 34368kbit/s port maximum allowable input jitter lower limit parameters
Bit rate
34368kbit/s
Jitter value
fo(Hz)
Frequency value of the sinusoidal signal that modulates the digital signal to produce jitter and drift (digital signal jitter frequency)
f1o(Hz)
fo(Hz)
[1:1-2) .1n
fe(Hz)
fi(Hz)
f2(kHz)
fa(kHz)
fa(kHz)
47777777747
Figure 2343688kbit/s port maximum allowable input jitter lower limit 5.1.1.4.4 Anti-interference requirements
Test
Pseudo-random
228-1
A useful signal and an interference signal are added to a mixed signal through a mixing network. The useful signal and the interference signal should comply with the provisions of Articles 5.1.1.1 and 5.1.1.3. The signal is a 223-1 pseudo-random sequence. The bit rates of the useful signal and the interference signal should be within the tolerance range specified in this standard, but should not be synchronized. The ratio of the useful signal to the interference signal is 20dB, and the nominal impedance of the hybrid network is 752 (coaxial). When the hybrid signal is added to the input port after the specified 0-12dB cable attenuation, there should be no bit errors. GB/T11324-1995
Note: It is possible to provide an adaptive rather than a fixed receiver, which can be considered to be more reliable in preventing reflections and should be used first. 5.1.2139264kbit/s connection
5.1.2.1Nominal bit rate: 139264kbit/sTolerance: ±15×10-,
Code type: CMI.
Overvoltage protection requirements: See Appendix A.
5139264kbit/s output port requirements: See Table 5 and Figure 3. 5.1.2.3
Table 5139264kbit/s output port - general requirements Nominal pulse shape
Line pairs in each transmission direction
Test load impedance
Pulse peak-to-peak voltage
Rise time of 10% to 90% of the measured amplitude
Conversion timing tolerance
(in negative direction Conversion average half amplitude point as the standard) Return loss
Rectangular (see Figure 3)
Coaxial line pair
75ΩResistance
<2ns
a. Negative conversion: ±0.ins
b. Positive conversion on the boundary of unit code element interval: ±0.5nsc. Positive conversion on the center of unit code element interval: ±0.35ns≥15dB (7~210MHz)
T =7. [a ns
Figure 3a corresponds to the pulse frame of binary "0" 1.706ns
Note: ①The maximum steady-state amplitude should not exceed 0.55V. Overshoot and other transient values are allowed to fall into the dotted area between 0.55 and 0.6V, that is, the part exceeding the steady-state value 5
should be less than 0.05V.
GB/T11324—1995
②Each pulse of the pulse code sequence should be within the limit of the frame, regardless of the state of the previous and next pulses. The pulse templates are fixed relative to the common reference time, that is, their leading and trailing edges are consistent. The template requires that the rise and fall times should be measured between 0.40.4V and should not exceed 2ns. T=I.JH9
Figure 3b corresponds to the pulse template of "binary 1" n.ins
Note: The maximum "steady-state" value should not exceed 0.55V, and overshoot and other transient values are allowed to fall into the dotted area between 0.55 and 0.6V, that is, the part exceeding the steady state should be less than 0.05V.
②Each pulse of the pulse code sequence should be within the limits of the template, regardless of the state of the previous and next pulses. The two templates are fixed relative to the common reference time, that is, their leading and trailing edges are consistent.③The template requires that the rise and fall times should be measured between 0.4 and 0.4V and should not exceed 2ns.④The reverse pulses should have the same characteristics, and the corresponding positive and negative edge levels are ±0.1V and ±0.5V. 5.1.2.4139264kbit/s input port requirements5.1.2.4.1 Input impedance
Nominal value: 752 (coaxial);
Input port impedance characteristics are shown in Table 6.
Table 6139264kbit/s input impedance characteristics
Frequency range, MHz
5.1.2.4.2 Permissible attenuation at the input port
Return loss, dB
GB/T11324—1995
The digital signal appearing at the input port shall comply with the provisions in Table 5, but it is allowed to vary depending on the transmission line pairs used to connect the output port and the input port, and the input port shall be able to adapt to these changes. The attenuation frequency characteristics of these line pairs shall approximately conform to the law, and the minimum change in the attenuation value at the 70MHz frequency point shall reach 0~12dB. This attenuation value shall include any attenuation introduced by the digital patch panel between the output port and the input port.
5.1.2.4.3 139264kbit/s input port jitter tolerance: see Table 7 and Figure 4. Table 7 139264kbit/s input jitter lower limit
Bit rate
139264kbit/s
Jitter value
5.2 Jitter
fo(Hz)
5.2.1 Jitter transfer characteristics
Frequency value of the sinusoidal signal that modulates the digital signal to produce jitter and drift (digital signal jitter frequency)
f1o(Hz)
fg(Hz)
J—7-FS||tt| |fe(Hz)
fi(Hz)
f2(kHz)
fs(kHz)
Solution*10
f,(kHz)
Figure 4139264kbit/s port maximum allowable input jitter lower limit test
Pseudo-random
-A 34368kbit/s signal modulated by sinusoidal jitter, which is affected by the jitter transfer characteristics of the multiplexer and demultiplexer, should be within the gain/frequency limit range shown in Figure 5. The equivalent binary content of the test signal is 1000.7
GB/T11324—1995
Figure 5 Jitter transfer characteristics
Note: ① Considering the limitations of the test instrument, f. should be as low as possible and should not be higher than 20Hz (such as 10Hz). ② In order to make the measurement accurate, the frequency selection method is used for measurement, and the frequency selection bandwidth shall not be wider than 40Hz. 5.2.2 Branch output jitter
When measuring at frequencies below 800kHz, the peak-to-peak jitter at the branch output should not exceed 0.3UI in the absence of input jitter.
When tested with an instrument equipped with a bandpass filter with a low-frequency cutoff frequency of 10kHz, a 20dB roll-off in a decade and an upper limit frequency of 800kHz, the peak-to-peak jitter at the branch output should not exceed 0.05UI with a probability of 99.9% within a test time of 10s. 5.2.3 Multiplexed signal output jitter
When the transmitted timing signal is obtained by the internal oscillator, the peak-to-peak jitter at the 139264kbit/s output should not exceed 0.05UI when tested in the frequency range of f1-200Hz to f4=3500kHz. 5.3 Timing signal
The timing signal of the multiplexer can be obtained from both external and internal sources. 5.4 Fault conditions and corresponding measures
5.4.1 Fault conditions
The digital multiplexing equipment should detect the following fault conditions: 5.4.1.1 Power failure.
5.4.1.2 The 34368kbit/s input signal at the input of the multiplexer disappears, 5.4.1.3 The 139264kbit/s input signal at the input of the demultiplexer disappears. Note: This fault is only required to be detected if it does not cause a loss of frame indication. 5.4.1.4 Loss of frame
5.4.1.5 An alarm indication is received from the multiplexing equipment at the other end at the 139264kbit/s input of the demultiplexer (see 3.4.2.2). 5.4.2 Corresponding measures
After the fault condition is detected, further measures as specified in Table 8 should be taken. The corresponding measures are as follows: 5.4.2.1 Issue an immediate maintenance alarm indication, indicating that the performance has fallen below the allowable standard and requiring this end to pay attention to maintenance. When the 139264kbit/s alarm indication signal is detected at the input end of the demultiplexer (see Note ② below), the immediate maintenance alarm indication related to the frame loss should be prohibited, and the remaining corresponding measures are still the measures related to the fault condition in Table 8. 5.4.2.2 Change the group I bit 13 of the 139264kbit/s output end of the multiplexer from state "0" to state "1", and issue an alarm indication to the multiplexing equipment at the other end.
5.4.2.3 Add AIS (see Notes ① and ② below) to all four 34368kbit/s branch outputs of the demultiplexer. 5.4.2.4 Add AIS (see Notes ① and ② below) to the 139264 kbit/s output of the multiplexer. 5.4.2.5 Add AIS (see Note ② below) to the 8
time slots corresponding to the relevant 34368 kbit/s branch in the 139264 kbit/s signal of the multiplexer.
GB/T11324—1995
The method of transmitting AIS at the output port of the multiplexer in the time slot corresponding to the faulty input branch should be able to control the state of the code rate adjustment service bit (C) to ensure that the bit rate of AIS is within the tolerance specified for the branch. Note: ① The bit rate of AIS at the output of the multiplexer and the output of the demultiplexer should be as specified in the respective interface specifications. ② The equivalent binary content of the 34368kbit/s and 139264kbit/s alarm indication signals should nominally be a series of 1s. Even when the bit error rate is 1×10-, its AIS can be detected, but signals in which all bits except the frame positioning signal are in the "1" state should not be considered as AIS. Table 8 Fault conditions and corresponding measures
Corresponding measures (see 5.4.2)
Equipment part
Multiplexer and
Demultiplexer only
Demultiplexer only
Fault condition
(see 5.4.1)
Power failure
Branch signal
Input signal disappears
Frame Loss of position
Receive alarm indication from the peer
multiplexing equipment
Issue immediate maintenance
alarm indication
Issue
alarm indication to the peer
multiplexing equipment
All branches
(if feasible)
Comprehensive signal
(if feasible)
Comprehensive signal
Related time slots
Note: "To" in the table means that measures should be taken in the relevant fault conditions, and "" means that in the relevant fault conditions, if the condition is unique, no corresponding measures need to be taken. If more than one fault condition occurs at the same time, and at least one of the fault conditions specifies the "to" measures to be taken, then the measures to be taken Relevant measures.
5.5 Reliability index
MTBF≥10 years.
6 Test method
6.1 Test conditions
6.1.1 Ambient temperature: 5~40℃.
6.1.2 Relative humidity: 85% (30℃).
6.1.3 Atmospheric pressure: 70106kPa.
6.1.4 Power supply voltage: -48V±20% or -60V+20% or -24V疆%. 6.2 Test instruments and test signals
The test instruments used shall be qualified by the second-level or above measurement units. Except for special circumstances, the test signal shall comply with the relevant provisions of Article 5.1. The test is carried out at the input and output ports of the equipment. 6 .3 The maximum allowable frequency deviation test of the branch input is connected as shown in Figure 6.
Test the branch circuit, increase (decrease) the clock frequency of the code generator to make the branch produce bit errors, and then adjust the clock frequency in the opposite direction to make it just no bit errors. The difference between the highest (lowest) frequency and the nominal frequency at this time is the maximum allowable frequency deviation. When the clock frequency of the multiplexed signal is not changed, the measured frequency deviation should be greater than 1209Hz, or when the clock frequency of the multiplexed signal is changed to 139264000 2089Hz, the measured frequency deviation should be greater than 687Hz. akblt/
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6.4 Master oscillation frequency test
Connect as shown in Figure 7.
34368hit/9
Test the allowable frequency deviation of the branch input
Figure? Master oscillation frequency test
139284khi/
1392kbi
Use a frequency counter to connect to the 139264kHz clock output terminal for testing, and its frequency should be within the range of 139264000±2089Hz. 6.5 Test of digital interface indicators
6.5.134368kbit/s output port pulse waveform test Connect according to Figure 8.
GB/T11324—1995
4 H kbit/s
135261611/5
136254kbit/sa
Figure 834368kbit/s output port pulse waveform test branch circuit for testing. Terminate the 34368kbit/s output port of the equipment with a 75Q resistor (accuracy 1%), select a high-frequency broadband oscilloscope (frequency>250MHz) and use a high impedance across the two ends of the terminal resistor for observation and testing. The output waveform should meet the requirements of Article 5.1.1.3.
6.5.2 34368kbit/s input port indicator test 6.5.2.1 34368kbit/s input port allowable attenuation test Connect according to Figure 9.
Only #
Figure 9 34368kbit/s input port allowable attenuation test 134 1/out
u ksa
branch line for testing. Connect the 34368kbit/s digital signal that meets the output interface index to the code generator and the branch input port through a cable that complies with the ~√ attenuation law and whose attenuation value is within the range of 012dB when the frequency is 17184Hz. The branch should be error-free. The attenuation value can be selected as 0dB, 6dB, and 12dB. If necessary, the attenuation value can be increased. 6.5.2.2 34368kbit/s input port return loss test is connected according to Figure 10.3 The maximum allowable frequency deviation test of the branch input is connected as shown in Figure 6.
Test the branch circuit, increase (decrease) the clock frequency of the code generator, so that the branch generates bit errors, and then adjust the clock frequency in the opposite direction to make it just no bit errors. The difference between the highest (lowest) frequency and the nominal frequency at this time is the maximum allowable frequency deviation. When the clock frequency of the multiplexed signal is not changed, the measured frequency deviation should be greater than 1209Hz, or when the clock frequency of the multiplexed signal is changed to 139264000 2089Hz, the measured frequency deviation should be greater than 687Hz. akblt/
Zhaoye card issuer
6.4 Master oscillation frequency test
Connect as shown in Figure 7.
34368hit/9
Branch input allowable frequency deviation test
Figure? Master oscillation frequency test
139284khi/
1392kbi
Use a frequency counter to connect to the 139264kHz clock output terminal for testing, and its frequency should be within the range of 139264000±2089Hz. 6.5 Test of digital interface indicators
6.5.134368kbit/s output port pulse waveform test Connect according to Figure 8.
GB/T11324—1995
4 H kbit/s
135261611/5
136254kbit/sa
Figure 834368kbit/s output port pulse waveform test branch circuit for testing. Terminate the 34368kbit/s output port of the equipment with a 75Q resistor (accuracy 1%), select a high-frequency broadband oscilloscope (frequency>250MHz) and use a high impedance across the two ends of the terminal resistor for observation and testing. The output waveform should meet the requirements of Article 5.1.1.3.
6.5.2 34368kbit/s input port indicator test 6.5.2.1 34368kbit/s input port allowable attenuation test Connect according to Figure 9.
Only #
Figure 9 34368kbit/s input port allowable attenuation test 134 1/out
u ksa
branch line for testing. Connect the 34368kbit/s digital signal that meets the output interface index to the code generator and the branch input port through a cable that complies with the ~√ attenuation law and whose attenuation value is within the range of 012dB when the frequency is 17184Hz. The branch should be error-free. The attenuation value can be selected as 0dB, 6dB, and 12dB. If necessary, the attenuation value can be increased. 6.5.2.2 34368kbit/s input port return loss test is connected according to Figure 10.3 The maximum allowable frequency deviation test of the branch input is connected as shown in Figure 6.
Test the branch circuit, increase (decrease) the clock frequency of the code generator, so that the branch generates bit errors, and then adjust the clock frequency in the opposite direction to make it just no bit errors. The difference between the highest (lowest) frequency and the nominal frequency at this time is the maximum allowable frequency deviation. When the clock frequency of the multiplexed signal is not changed, the measured frequency deviation should be greater than 1209Hz, or when the clock frequency of the multiplexed signal is changed to 139264000 2089Hz, the measured frequency deviation should be greater than 687Hz. akblt/
Zhaoye card issuer
6.4 Master oscillation frequency test
Connect as shown in Figure 7.
34368hit/9
Branch input allowable frequency deviation test
Figure? Master oscillation frequency test
139284khi/
1392kbi
Use a frequency counter to connect to the 139264kHz clock output terminal for testing, and its frequency should be within the range of 139264000±2089Hz. 6.5 Test of digital interface indicators
6.5.134368kbit/s output port pulse waveform test Connect according to Figure 8.
GB/T11324—1995
4 H kbit/s
135261611/5
136254kbit/sa
Figure 834368kbit/s output port pulse waveform test branch circuit for testing. Terminate the 34368kbit/s output port of the equipment with a 75Q resistor (accuracy 1%), select a high-frequency broadband oscilloscope (frequency>250MHz) and use a high impedance across the two ends of the terminal resistor for observation and testing. The output waveform should meet the requirements of Article 5.1.1.3.
6.5.2 34368kbit/s input port indicator test 6.5.2.1 34368kbit/s input port allowable attenuation test Connect according to Figure 9.
Only #
Figure 9 34368kbit/s input port allowable attenuation test 134 1/out
u ksa
branch line for testing. Connect the 34368kbit/s digital signal that meets the output interface index to the code generator and the branch input port through a cable that complies with the ~√ attenuation law and whose attenuation value is within the range of 012dB when the frequency is 17184Hz. The branch should be error-free. The attenuation value can be selected as 0dB, 6dB, and 12dB. If necessary, the attenuation value can be increased. 6.5.2.2 34368kbit/s input port return loss test is connected according to Figure 10.
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