This specification specifies the detailed requirements for the semiconductor integrated circuit Jμ8255A type programmable peripheral interface (hereinafter referred to as the device). This specification applies to the development, production and procurement of the device. SJ 20074-1992 Semiconductor Integrated Circuit Jμ8255A Type Programmable Peripheral Interface Detailed Specification SJ20074-1992 Standard download decompression password: www.bzxz.net

Military Standard of the Electronic Industry of the People's Republic of China SJ 20074--92
Semiconductor Integrated Circuits
Ju8255A Programmable Peripheral Interface
Detailed Specification
1992-11-19 Issued
1993-05-01 Implementation
Issued by the Ministry of Machinery and Electronics Industry of the People's Republic of China 1 ScopebzxZ.net
1.1 Title
1.2 Scope of application
1.3 Classification...
2 References
3 Requirements
3.1 Detailed requirements
3.2 Design, structure and dimensions
3.3 Lead materials and coating.
Electrical characteristics -
Electrical test requirements
Division of microcircuit groups
Quality assurance provisions
Sampling and inspection||tt ||Identification inspection
Quality consistency inspection
Inspection method
5 Delivery preparation
5.1 Packaging requirements
6 Notes
General provisions on test quantity
Ordering information
6.3 Functional description, symbol definition
6.4 Substitution
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People's Republic of China Electronic Industry Military Standard Semiconductor Integrated Circuits
Ju8255A Type Programmable Peripheral Interface Detailed Specification 1 Scope
1.1 Subject content
SJ 20074--92
This specification specifies the detailed requirements for the semiconductor integrated circuit Ju8255A type programmable peripheral interface (hereinafter referred to as the device).
1.2 Scope of Application
This specification applies to the development, production and procurement of microcircuits. 1.3 Classification
This specification classifies microcircuits according to device model, device level, packaging form, rated value and recommended operating conditions. 1.3.1 Device Number
The device number shall comply with the provisions of Article 3.6.2 of GJB597 "General Specification for Microcircuits" 1.3.1.1 Device Model
Device Model:
Device Model
Ju8255A
1.3.1.2 Device Level
Device Name
Programmable Peripheral Interface
The device level is Class B as specified in Article 3.4 of GJB597 and Class B1 as specified in this specification. The provisions in this specification that do not specify Class B1 shall be understood as the same as Class B. 1.3.1.3 Packaging form
The packaging forms are as follows:
Packaging form!
D40L3 (40-lead ceramic dual-in-line package)
C44P3 (ceramic leadless chip carrier package) Note: 1) According to GB7092 "Outer dimensions of semiconductor integrated circuits". 1.3.2 Absolute maximum ratings
The absolute maximum ratings are as follows:
Approved by the Ministry of Machinery and Electronics Industry of the People’s Republic of China on November 19, 1992 and implemented on May 1, 1993
Voltage of any lead terminal relative to the Vss terminal
Storage temperature range
Lead soldering temperature (5s)
Junction temperature (Tc-125°C)
1.3.3 Recommended operating conditions
The recommended operating conditions are as follows:
Power supply voltage
Input quotient level voltage
Input low level voltage
Case operating temperature range
Referenced documents
SJ 20074--92
GB3431.1-82 Non-conductor integrated circuit text symbols Electrical parameter text symbols GB3431.2-86 Semiconductor integrated circuit text symbols: Terminal function symbols GB4590-84 Mechanical and climatic test methods for semiconductor integrated circuits GB7092--93 Dimensions of semiconductor integrated circuits GJB548-88 Test methods and procedures for microelectronic devices GJB597-88 General specifications for microcircuits
GJB/Z105 Electronic product anti-static discharge control manual 3 Requirements
3.f Detailed requirements
All requirements shall comply with the provisions of GJB597 and this specification. 3.2, Design, structure and dimensions
The design, structure and dimensions shall comply with the provisions of GJB597 and this specification. 3.2.1 Terminal arrangement
The terminal arrangement shall comply with the provisions of Figure 1. The terminal arrangement is a top view. - 2 -
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Chao Tao Ya Tao Fu
SJ20074—92
ERESET
Chip carrier package terminal arrangement
Figure 1 Terminal arrangement
3.2.2 Functional block diagram
The functional block diagram should comply with the provisions of Figure 2.
39 PAS
35 RESET
34 DO
32 D2
31 D3
25 PB7
24 PB6
22 PB4
21 PB3
Dual in-line package lead arrangement
Dual number
Data bus
D0~ D7
Data bus
3.2.3 Functional description, symbols and definitions
SJ 20074—92
Figure 2 Functional diagram
The functional description, symbols and definitions shall comply with the provisions of Article 6.3 of this specification. 3.2.4 Package form
The package form shall comply with the provisions of Article 1.3.1.3 of this specification. 3.3 Lead materials and coating
Lead materials and coating shall comply with the provisions of GJB597 Section 3.5.6. 3.4 Electrical characteristics
Intersection B
Electrical characteristics shall comply with the provisions of Table 1. If there are no other provisions, they are suitable for the full operating temperature range. 3.5 Electrical test requirements
PAO~PA?
PC4~PC7
PC0~PC3
PB0~PB7
The electrical test requirements for each level of devices shall be the relevant divisions specified in Section 2, and the splash test for each group shall comply with the provisions of Table 3.
3.6 Labeling
Marking shall comply with the provisions of GJB597 Section 3.6. 3.7 Division of micro-outlet groups
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The device involved in this specification is the 107th microcircuit group (see Appendix E of GJB597), electrical characteristics
Input low voltage
Input high voltage
Output low voltage
(data bus)
Output low voltage
(peripheral port)
Output high voltage
(data bus)
Output high voltage Level voltage
(peripheral end)
Darlington drive current
(B and C ports)
Power supply current
Input load current
High impedance leakage current
Input capacitance
Input/output capacitance
Address establishment time before read signal
Time after read signal ends
Address hold time
Read pulse width||tt| |Data valid delay time
time (starting from READ
)
Read signal to data bus floating time
Time interval between two read or write signals
Address establishment time before write signal
YoL(DB)
VOL(FBR)
YOH(H)
VOH(PER)
IguAAV-RL)
Th(RII-AX)
ta(RL-DX)
Fgu(AV-WL)
Article 2)
loL=2.5 mA
foL=1.7mA
foH=-400μA
ToH=-200μA
V-Vop to ov
Vo-Ypp to 0.45 V
Te=25 °c, Ypp=0 V,
F-1MRz
Tc=25 \C,Ypp -0 V,
1 MHz, unterminated to ground
Ci-100 pF
Specification value
Sequence number 1
Write signal ends at ground
Address hold time
Write pulse width
Time from data valid to the end of the pulse
Temporary data guarantee time after the end of the write signal
WR-1 To output
External data before RD
Input time
External data after RD
Hold time
ACK pulse width
STB pulse width
hWH-AX)
fwiwL)
Tsu(DV-WH)
th(WH-DV)
farwH-ovy
su(1V-RL
thRH-Ix)
fwrACRL)
TW(acKL)
External before STE ends
ta(PERV-STRH)
Data setup time
External 4bSTBH-PERZ) after STB ends
Data hold time
From ACK-0
Delay time from ACK-1 to output
delay time from WR-1 to
OBF = 0
Delay time from ACK-0 to
OBF=I
Delay time from STB-0 to
IBF=1
Delay time from RD-I1 to
IBF=0
Delay time from RD-O to
INTR-0 When delayed
taiACKL-PERVI
ta[ACKH-PERZ)
Fa(WH-ORFT.
d(ACKL-OBFH)
f&(STBL-IBFH)
a(RH-FBFL)
fd(RL-INTRL)
SJ 20074-92
Continued Table 1
Condition 2)
Ct=100 pF
Cr=[00 pF
Ch=100 pF
Specification value
10, 11
10, 11
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Serial number 0
from STB-1 To
[NTR-1 delay time
From ACK-1 to
INTR=|send time
From WR=1 to
INTR-O delay
++(STBH-INTRH)
tHACKH INTRH!
fd(WL-INTRL)
SJ20074—92
Continued Table 1
Condition 2)
CL=100 pF
method: 1) The serial number of the parameters in this table is consistent with the serial number of the parameters in the timing diagram; 2) If other provisions, Tm ~ 55-~ 125n center, Vuu = 5 ± 0.5V, Vss = V Table 2 Test requirements
Test requirements
Intermediate (before aging) Other test (Method AI, A75004)
Final electrical test 1)
(Method 5004)
A Red Test requirements 2)
(Method 5005)
Group B VZAp Test
Group C endpoint test
(Method 5005)
Group C inspection added group
Group D endpoint electrical test
(Method 5005)
Grade B devices
Current specification values
Groups (see Table 3)
Grade B1 devices
A1, A2. A3, A7,A8, A9, A10, A1, A2, A3, A7, A9A11
A1,A2, A3,A4,A7,A8,A9,
See 4.5.3 of this specification
A2. A3, A8
Not required
A2, A8 (125°C only)
Note: 1) A1. The A7 group requires PDA calculation (see clause 4.2 of this specification). 2A4 Group (C, () instrument is used for identification (see 4.4.1 of this specification) waveform
Al, A2. A3, A4, A7. A9
See 4.5.3 of this specification
A2, A8 (only 125 PC)
A2,A8 (only 125 cC)
VOLPER?
YOEIDB)
VOH(FEHi
SJ20074-—92
Table 3A Group Test
foL -2.0 rmA
foL =1.7 mA
IoH =400 μA
1OH=-200 μA
F=Vp to 0V
Vo - Vp to 0.45 V
Xu Tc=125°C, parameters, conditions, and specification values ​​are the same as group A1: except Tc=-55 \C, parameters, conditions, and specification values ​​are the same as group A1. G
Vpn=0 V, f=1 MHz
Vp=0 V, f-1 MHz not tested
terminal grounded
Specification value
Tc=25 ℃C, according to 6.2, functional test is carried out at VpD =4.5 V and YpD-5.5 V respectively, except Tc-[25°℃ and -55°℃: same as group A7 L13
Esu AV-RL
FhRH-AXI
taiRL-DX
tdiRH-DZI
fsurAV-WL)
FhWH-AXI
furwH- on
LsuY-RL)
TWiACKLI
w(STBL)
FePERV-STHHS
(STBH-PERZ)
Ci=100 pP
Gj=100 pF
8, 12
10, 11
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Fa(ACKIL-PERY)
tt(ACKH-PERZ)
SJ 20074—92
ContinuedTable 3
Ch=100 pF
CL=100 pF
TaCWEL-OBFLL
L&ACKL-OBTH!
Ld(STBL-IBFH)
drRH-IBEL)
ta(RI-INTRL.)
LaISTBE-INTRH)
d(ACKH-INTRH)
TINTRL)
Except Tc-125°C, the parameters, conditions and specification values ​​are the same as those of group A9. Except Tr-55 ℃, the parameters, conditions and specification values ​​are the same as those of group A9. Power supply
Note: ①RI takes appropriate current limiting voltage:
?CJ=100pF±20%:
③VzAP=400V, measured at the device input: ③Pulse conversion time (tTtH) ≤50ns (10%～90%), specification value
Figure 3 High voltage (VzAp) test circuit
Connect the device under test
10, 11
SJ 20074—92
Note: @The lead end PA0~PA7 adds a wave with a frequency of 1kHz: ②The lead end D0~D7 is connected to a 150pF capacitor:
②The lead end RESET is set to "I\" at the beginning, and then grounded. 40
Figure 4 Aging and life test circuit diagram
- 10 -
Test point
AC test input/output waveform
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SJ 20074—92
Note: @A wave with a frequency of 1kHz is applied to the lead terminals PA0~PA7: ②Connect 150pF capacitors to the lead terminals D0~D7:
②At the beginning, the lead terminal RESET is set to "I\" and then grounded. 40
Figure 4 Aging and life test circuit diagram
- 10 -
Test point
AC test input/output waveform diagram
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