title>GB/T 3455-1982 Electrical characteristics of unbalanced dual-current interface circuits - GB/T 3455-1982 - Chinese standardNet - bzxz.net
Home > GB > GB/T 3455-1982 Electrical characteristics of unbalanced dual-current interface circuits
GB/T 3455-1982 Electrical characteristics of unbalanced dual-current interface circuits

Basic Information

Standard ID: GB/T 3455-1982

Standard Name: Electrical characteristics of unbalanced dual-current interface circuits

Chinese Name: 非平衡双流接口电路的电特性

Standard category:National Standard (GB)

state:in force

Date of Release1982-01-02

Date of Implementation:1983-10-01

standard classification number

Standard ICS number:Telecommunications, audio and video technology>>Telecommunications systems>>33.040.50 Lines, connections and circuits

Standard Classification Number:Electronic Components and Information Technology>>Information Processing Technology>>L78 Data Information

associated standards

Procurement status:≈CCITT V28

Publication information

publishing house:China Standards Press

Publication date:1983-10-01

other information

Release date:1982-12-31

Review date:2004-10-14

Drafting unit:Standard Drafting Working Group

Focal point unit:National Information Technology Standardization Technical Committee

Publishing department:National Bureau of Standards

competent authority:National Standardization Administration

Introduction to standards:

The electrical characteristics specified in this recommendation are applicable to interface circuits operating at data signal rates below the limit of 20,000 bits/second. This standard is technically safe and consistent with CCITT Recommendation V.28. GB/T 3455-1982 Electrical characteristics of unbalanced dual-stream interface circuits GB/T3455-1982 Standard download decompression password: www.bzxz.net

Some standard content:

National Standard of the People's Republic of China
Electrical characteristics for unbalanced double - current interchange circuitsUDC 621.316.
GB3455-52
The electrical characteristics specified in this recommendation are applicable to interface circuits operating at data signal rates below the limit of 20,000 bits/second. This standard is completely consistent with CCITT Recommendation V:28 in terms of technology. 2 Interface equivalent circuit
The interface equivalent circuit shown in Figure 1 and its electrical parameters are defined as follows. Whether the generator is located in the data circuit terminating equipment, the load is located in the data terminal equipment, or vice versa is irrelevant to this equivalent circuit.
The impedance associated with the generator (load) includes any cable impedance on the generator (load) side of the interface point. The equipment on both sides of the interface can be implemented on the receiver of the generator or any combination of types. Interface point
Generator
Building circuit
Signal ground or common return
(Circuit 102 or 201)
Interface equivalent circuit
Figure 1, V—Open circuit voltage of generator:
R4—Total effective DC resistance related to the generator measured at the interface point: Co—Total effective capacitance related to the generator measured at the interface point: V, Voltage at the interface point to the signal ground or common return line: C,—Total effective capacitance related to the load measured at the interface point, RL—Total effective DC resistance related to the load measured at the interface; E. Load open circuit voltage (bias voltage).
National Bureau of Standards 1982-12-31 Issued
CCTT43641
1983-10~01 Implementation
GB3455-82
When used for data transmission, it is generally believed that the interface cable should be provided by DTE. In this way, there is a dividing line between DTE plus the cable and DCE. This line is also called the interface point, and it is specifically implemented in the form of a connector. This type of application also requires interface circuits in both directions. This leads to the situation shown in Figure 2. Connector
Signal ground
T'E plus cable
Boundary practice
The actual embodiment of the interface in Figure 2
Towards: () If there is a requirement in national regulations, the signal ground can be further connected to the external protective ground wire. DCE
② For data transmission on live facilities, ISD specifies a 25-pin connector and its pin assignments according to ISO 2110 [1]. Load
The test conditions for measuring load impedance are shown in Figure 3. The impedance on the load side of the interface circuit should have a DC resistance (RL) between 3000 and 7000 ohms. When a voltage (Em) of 3 to 15 volts is applied, the measured input current (I) should be within the following range: Em±ELmax
Imin, mx
The load open circuit voltage (E1.) should not exceed 2 volts. Rimaz, mla
Test equipment
GB 6455-82
Interface point
Connected circuit
Common common circuit
Figure 3 Equivalent test circuit
The effective load capacitance measured at the interface point should not exceed 2500 pF. Load
CCITT - 43661
In order to avoid induced voltage surges (electric shock) in the interface circuit, the reactance component of the load impedance should not be inductive. Note: This point is still for further study.
The load on the interface circuit should not affect the continuous operation of any input signal, and the voltage of the signal should be within the limits specified in 4 below. Generator
The generator on the interface circuit should be able to withstand open circuits and short circuits between it and any other interface circuit (including the generator and the load) without damaging itself or its related equipment. The open circuit voltage (V) of the generator on any interface circuit shall not exceed 25 volts. The impedances (R. and C.) on the generator side of the interface circuit are not specified, however, the combination of R. and R. shall be chosen so that a short circuit between any two interface circuits will not produce a current exceeding 0.6 amperes under any circumstances.
In addition, for any load resistance (RL) in the range of 3000 to 7000 ohms, the voltage (V) at the interface point shall not be less than 5 volts nor greater than 15 volts (regardless of positive or negative polarity) when the open circuit voltage (EL) of the load is zero. The effective shunt capacitance (C.) of the interface circuit on the generator side is not specified. However, in addition to any load resistance (R.), the generator shall be able to drive the total capacitance of the capacitance on the generator side (C.) plus the load capacitance (CL) of 2500 pF. Note: Relays or switch contacts may be used to generate the signals on the interface circuit, and appropriate measures shall be taken to ensure that the signals generated comply with the provisions of the following clause 6.
5 Effective level (V1)
For data interface circuits, when the interface circuit voltage (V1) measured at the interface point is lower than -3 volts, the signal should be judged as binary "1" state. When the voltage (V) is higher than +3 volts, the signal should be judged as binary "0" state. For control and timing interface circuits, when the voltage (V1) of the interface circuit is higher than +3 volts, the circuit should be judged as "on", and when the voltage (V1) on the interface circuit is lower than -3 volts, the circuit should be judged as "off" (see Table 1). , the internal resistance of the ammeter should be much smaller than the load resistance (R1). 6
< - 3 state
GB3455-82
Table phase watt relationship table
V>+3 advantage
In some countries, when the instrument is directly connected to a DC telegraph circuit, the polarity of the voltage in Table 1 can be reversed. → The region between 3 volts and -3 volts is defined as the transition region. See 7 for differences. Signal Characteristics
The characteristics of the signal transmitted through the interface point are subject to the following restrictions. When the interface circuit is connected to a receiving circuit that meets the characteristics specified in 13, these restrictions shall also be met at this connection point, but external interference is not included. Unless otherwise specified, these restrictions shall apply to all interface signals (data, control and timing). 3.1 All interface signals that enter the transition region shall continue to traverse this region to reach the desired signal state and shall not re-enter this region before the next valid signal state change, except as shown in 6.6 below. 3.2 When the signal is in the transition region, the direction of the voltage change shall not change, except as shown in 6.6 below. 6.3 For the control interface circuit, the time required for the signal to pass through the transition region when the state changes shall not exceed -milliseconds. 6.4 For data and timing circuits, the time required for the signal to pass through the link change area when the state changes shall not exceed 1 millisecond, or shall not exceed 3% of the nominal code light period on the circuit, whichever is smaller. 6.5 In order to reduce the occurrence of interference between interface circuits, the maximum instantaneous rate of change of voltage shall be limited. The temporary limit is set at 30 volts/microsecond.
6.B When using electromechanical equipment on the circuit, the two points 6.1 and 6.2 on the upper mountain are not suitable for the circuit. Detection of generator output or output failure
Some applications require detection of various fault conditions in the circuit, such as: a: Generator power-off state!
h The receiver is interconnected with the generator:
Cable circuit
d. The short-circuited cables shall have an open impedance of not less than 300 ohms on the generator side of these circuits when tested with an applied voltage (positive or negative polarity) not greater than 2 volts referenced to signal ground or common return. The interpretation of the fault condition by the receiver (or load) depends on the application. Each application may use a combination of the following categories: Type Gate: No interpretation. Receiver or load has no detection capability. Type 1: Data circuits assume the binary 1 state. Control and timing circuits assume the "off" state. The association of circuit fault detection with specific interface circuits conforming to the above types is a matter of functional and protocol characteristic specifications for the interface.
In the public telephone network interface, the interface circuits that monitor the circuit fault condition see V.24 Recommended explanation. References:wwW.bzxz.Net
【1】Data communication—25-core DTE/LCE interface connector and pin assignment, ISO standard 2110 (1980) = GB3455-82
Additional explanation:
This standard was proposed by the national standard drafting working group of "Basic Control Regulations for Data Communication". The main drafters of this standard are Ma Shuxiao, Wang Qinsheng, Zheng Maohong, Ye Shaozhi, Zhu Min, Zhang Wenhui, Zhang Qingfan, Zhang Baodong, Yao Shiquan, and Cheng Tiande.
Tip: This standard content only shows part of the intercepted content of the complete standard. If you need the complete standard, please go to the top to download the complete standard document for free.