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SJ 20777-2000 Electronic Design Hardware Description Language VHDL

Basic Information

Standard ID: SJ 20777-2000

Standard Name: Electronic Design Hardware Description Language VHDL

Chinese Name: 电子设计硬件描述语言VHDL

Standard category:Electronic Industry Standard (SJ)

state:in force

Date of Release2000-10-20

Date of Implementation:2000-10-20

standard classification number

Standard Classification Number:>>>>L0137

associated standards

Procurement status:IEEE std 1076-1993 MOD

Publication information

publishing house:Industrial Electronics Press

Publication date:2000-10-20

other information

drafter:Li Yushan, Lai Xinquan, Cai Gushun, Yang Gang, Li Xianrui, etc.

Drafting unit:Xidian University

Focal point unit:China Electronics Standardization Institute

Publishing department:Ministry of Information Industry of the People's Republic of China

Introduction to standards:

This standard specifies the hardware description and design language (VHDL) specifications for electronic systems and circuits, especially digital integrated circuits, in the process of electronic automation design and manufacturing. This standard is applicable to the design of electronic, computer and communication electronic products, including electronic information systems, electronic circuits and various electronic products, especially the design of digital integrated circuits. When electronic design automation (EDA) tools are used for design, it is used as a standard in the following occasions: a. Simulation, synthesis, verification and testing of digital integrated circuits; b. Description of various complex electronic designs at the system level, printed circuit board (PCB) level, chip level, register transfer level and gate level; c. Behavioral level, structural level and data flow description of electronic circuits and electronic systems; d. Design data exchange between EDA tools or designers. SJ 20777-2000 Electronic Design Hardware Description Language VHDL SJ20777-2000 Standard download decompression password: www.bzxz.net

Some standard content:

Military Standard of Electronic Industry of the People's Republic of China FL0137
SJ 20777—2000
Electronic design hardware description language VHDL
Published on October 20, 2000
Implemented on October 20, 2000
Approved by the Ministry of Information Industry of the People's Republic of China Foreword
This standard is equivalent to the American Institute of Electrical and Electronics Engineers standard IEEEstd1076-1993IEEEStandardVHDLanguageReferenceManual", which is the IEEE std 1076-1987, so the technical content is consistent.
According to the "Interim Provisions on the Compilation of National Military Standards", major changes have been made to the format to make it more organized. The specific changes are as follows:
a. The contents of Chapter 1, Chapter 2 and Chapter 3 have been added: b. Chapter 2 corresponds to Appendix E of the original standard and supplements the cited national standards; c. Chapter 3 corresponds to Appendix B of the original standard: d. Chapter 4 corresponds to Chapter 0 of the original standard e. Article 5.1 of Chapter 5 corresponds to Chapter 1 of the original standard, Article 5.2 corresponds to Chapter 2 of the original standard, and so on, Article 5.14 corresponds to Chapter 14:
f. Appendix B corresponds to Appendix C of the original standard, and Appendix C corresponds to Appendix D of the original standard g. This standard has deleted the English index part of the original standard and deleted the publication statement Note: h For the sake of accuracy and domestic convenience, in Chapter 3 and Appendix A, Chinese and English translations of key terms are given.
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1 Scope
1.1 Subject content
1.2 Scope of application
2 Reference documents
3 Definitions
4 Overview
4.1 Purpose of this standard
4.2 Structure and terminology of this standard
4.2.1 Syntactic description
4.2.2 Semantic description
4.2.3 Examples, notes, references
5 Detailed requirements
5.1 Design entity and configuration
5.1.1 Entity description
5.1.2 Construct
5.1.3 Configuration description
5.2 Subroutines and Collection Packages
5.2.1 Subroutine Specification
Subroutine Body
Subroutine Overloading
5.2.4 Resolution Function
Collection Package Specification
Collection Package Body
Consistency Rules
5.3 Types
Scalar Types
Compound Types
Access Types
File Types
5.4 Specification
Type Specification
Subtype Specification
Attribute Specification
Component Specification
Group Template Specification
Group Specification
5.5 Specification
5.5.1 Attribute Specification
5.5.2 Configuration Specification
5.5.3 Separation Specification
5. 6 Name
5.6.1 Name
5.6.2 Short name...
5.6.3 Selection name
Subscript name
Fragment name
5.6.6 Attribute name
5.7 Expression...
Expression
Operator
5.7.3 Operand
5.7.4 Static expression||t t||5.7.5 General Expressions
5.8 Sequential Statements…·
5.8.1 Wait Statement
5.8.2 Assert Statement
5.8.3 Report Statement
Signal Assignment Statement
Variable Assignment Statement
5.8.6 Procedure Call Statement
5.8.7 If Statement*
5.8.8 Case Statement
5.8.9 Loop Statement
5.8.10 Next Statement
5.8.11 Exit Statement
5.8.12 Return Statementbzxz.net
5.8.13 Null Statements
5.9 Concurrent statements...
5.9.1 Block statements
5.9.2 Process statements
5.9.3 Concurrent procedure call statements
5.9.4 Concurrent assertion statements...
5.9.5 Concurrent signal assignment statements
5.9.6 Component instance creation statements
Creation statements·
Scope or Availability
5.10.1 Declaration area
5.10.2 Scope of declaration
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5.10.3 Availability
5.10.4 Use clause·
5.10.5 Context of overload resolution
Design unit and its compilation
Design unit·
Design library| |tt||Context clauses
Order of compilation,
5.12 Validation and execution
Design level validation
Block header validation
Description part validation
Statement part validation
Dynamic validation
Model execution
Lexical elements
Character set
Lexical elements, delimiters, and qualifiers
Identifiers
Abstract literals
Character literals
String literals
Bit string literals
Reserved words
5.13.10 Character interchangeability
5.14 Predefined locales
Predefined attributes
STANDARD package
5.14.3 TEXTIO collection package
Appendix A Summary of nomenclature (reference)
Appendix B Potentially non-portable structures (reference)Appendix C Differences between this standard and VHLD-1987 (reference)Center
Military standard of the electronics industry of the People's Republic of China Electronic design hardware description language VHDL
Electronic design hardware description language VHDL1 Scope
1.1 Subject content
SJ 20777--2000
This standard specifies the hardware description and design language (VHDL) specification for electronic systems and circuits, especially digital integrated circuits in the process of electronic automation design and manufacturing. 1.2 Scope of Application
This standard applies to the design of electronic, computer and communication electronic products, including electronic information systems, electronic circuits and electronic products, especially the design of digital integration: When electronic design automation (EDA) tools are used for the above design, it is used as a standard in the following occasions: a. Design simulation, synthesis, verification and testing of digital integrated circuits; b. Description of various complex electronic segments at the system level, printed circuit board (PCB) level, chip level, register transfer level and gate level;
G. For electronic circuits and Electronic systems are described at the behavioral level, structural level and data flow: d. Design data exchange between EDA tools or designers, 2 Reference documents
GB1988-1998 Information technology seven-bit coded character set GB/T15273.1--1994 eight-bit single-byte coded graphic character set 3 Definition
The standard adopts a large number of terms and phrases to describe the VHDL language, which are defined as follows: 3.1 Abstract text abstracttiteral
Text of general real abstract type or general integer abstract type. 3.2 Access type accesstype
The type that provides access to the specified type of object. Access to this object is completed by the access value returned by the allocator, and the access value is considered to indicate the object.
3.3 Access mode accessmode
The mode in which the file object is opened. It can be either read-only or write-only. The access mode depends on the value provided to the Open Kind parameter.
3.4 Access value acess value
TKAorKAca issued by the Ministry of Information Industry of the People's Republic of China on October 20, 2000
Implementation on October 20, 2000
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The value of the access type. This value is returned by the allocator and identifies an object of the specified type (must be a variable). A null access value does not identify any object. An access value can only identify an object generated by an allocator; it cannot identify an object described by an object description.
3.5 Active driven During a simulation cycle, whether a new value is different from the previous value and a new drive is required 3.6 Actual parameter actual
Expressions, ports, signals and variables associated with formal ports, formal parameters and formal categories. 3.7 Aggregate
a: This expression expresses a value of a composite type, which is specified by specifying the value of each element of the composite type. Positional association and name association may be used to indicate which value is associated with which element. b. The target of a variable assignment statement or a signal assignment statement that assigns a composite value. The target is considered to be the state of a set.
3.8 Alias ​​alias
Another name for a named entity.
3.9 Allocator
Operation on the generation of anonymous, variable objects accessible by access values. 3.10 Compilation analysis
Insertion of the syntax and semantics of source code in a VHDL design file and the medium for composing expressions of design units into a design library.
3.1f anonymous
An undefined abbreviation for an item is implicitly generated. The base type of a numeric type or an array type is anonymous. Similarly, the object represented by an access value is anonymous.
3.12 Appropriate
If the type of the prefix is ​​the type in question or the type of the prefix is ​​the access type (whose designated type is the type in question). Prefixes are considered appropriate for a type.
3.13 Architecturebody
The body associated with an entity declaration describes the internal organization or operation of a design entity. Constructs are used to describe the behavior, data flow, and structure of a design entity. 3.14 Arrayobjectarrayobject
An object of array type.
3.15 Arraytypearraytype
A type whose values ​​consist of elements of the same subtype (and therefore of the same type). Each element is uniquely distinguished by a subscript (for one-dimensional arrays) or a sequence of subscripts (for multidimensional arrays), each of which must be a value of a discrete type and must be in the correct subscript range.
3.16 Ascending rangingAscending rangingA range that increases from left to right.
3. 17 ASCI
American Standard Code for Information Interchange. The Standard and Collection Package includes definitions of type characters, the first 128 of which represent the values ​​of the ASCII character set.
3.18 Assertion violationSJ 20777—2000
A violation occurs when the conditional operation of an assertion statement evaluates to false. 3.19 Associated driver The only driver of a signal in a process statement containing a signal assignment statement. 3.20 As5ociated'in whole When a single associated element of a composite form provides an association for the entire formal parameter. 3.21 Individually associated associated individually The characteristics of a composite type parameter of a port, class, or relative to some association list. A composite formal parameter whose association is defined by multiple association elements in a single association list is considered to be a single association in that association list. The format of such an association element must express non-overlapping sub-elements or fragments of a formal parameter. 3.22 Association element association elemernt An element that associates an actual parameter or a local with a local or formal parameter. 3.23 Association list association List A list that establishes correspondence between a formal parameter, a local port parameter name, and a local, actual parameter name, or expression. 3.24 attribute
a definition of some characteristic of a named entity. Some attributes are predefined for type, range, value, signal, and function; others are user-defined and are always constants. 3.25 base specifier a lexical element indicating whether a bit string literal is to be interpreted as a binary, octal, or hexadecimal value. 3.26 basetype
a type for a subtype that defines a subset of possible values, or constraints. This subset is not required to be intrinsic: the base type of a type is the type itself. The base type of a subtype is established by recursively examining the type tokens in the subtype denotation that defines the subtype. If the type token expresses a type, that type is the base type of the subtype. Otherwise, the type token is the subtype. The process is repeated for that subtype. See also "subtype" 3.27 based literal
an abstract literal expressed in a form that explicitly specifies the radix. The radix is ​​restricted to be between 2 and 16. 3.28 basic operation basic operation An operation that has one of the following inherent properties: a. Assignment (in an assignment statement or initialization). b. Allocator. c. Selection name, subscript name, or fragment name. d. Qualification (in a qualification expression), explicit type conversion, parameter or argument identifier in a type conversion state, and implicit type conversion from an integer or common real type value to another numeric type: or e. A numeric literal (for common types), the literal null (for access types), a string literal, a bit string literal, a collection, or a predefined attribute. 3.29 basic signal basic signal A signal that determines the driving value of all other signals. A basic signal is either a scalar signal or a resolve signal. It is not a child of a resolve signal.
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SJ20777--2000
一 is not an implicit signal of the form SSta3le(T),S'Qwiet(T)成s\Transaction. 一 is not an implicit signal GUARD.
3.30 belongs to (a range) belang(toarange) The property of a value relative to a range. A value V is considered to belong to a range if both the relations (lower bound <= V) and (V <= upper bound) hold. The lower bound and upper bound are the lower and upper bounds of the range, respectively. (5.3.1, 5.3.2.1) 3.31 belongs to (a subtype) belong(taasubtype) The property of a value relative to a subtype. A value is considered to be a subtype of a specified type if it belongs to this type and satisfies the applicable constraints.
3.32 bindingbinding
The process of associating design entities and optional constructs with elements as instances. Bindings can be specified in explicit or default binding directives.
3.33 bitstring literal A literal consisting of a series of extended digits enclosed between two quote (") characters and following a base classifier. The type of a bitstring literal is determined by the context.
3. 34 block
An expression for a portion of a design hierarchy. A block can be either internal or external.3.35 bound
A label identified in a configuration-specific instance generation list.3.36 box
A symbol () in a subscript subtype definition that expresses an undefined range. Different objects of a type do not necessarily have the same boundaries or orientation.
3.37 bus
A guard signal. When all bus drivers are turned off, the bus drifts to a user-specified value.3.38 character literal A literal of character type. A character literal consists of a graphic literal (including space and non-breaking space characters) enclosed between two apostrophe (\) characters.
3.39 character type character type
An enumeration type. There must be at least one character literal in its enumeration literal. 3.40 CloselyTelatedtypes Two type tags that express the same type or two numeric types. If two array types have the same dimensions, their subscript types are closely related everywhere, and the array types have the same element type, then the two array types are closely related. Explicit type conversions are allowed only between closely related types. 3.41 Completion complete
Completes the execution of a laop. Similarly, a loop is completed when the while alternative evaluates to FALSE or when all discrete ranges of values ​​are assigned to the alternative parameters of a for alternative. 3.42 Completecontext A declaration, specifying, statement, complete context used for reload resolution. 3.43 Compositetype compositetype
A value that has the type of its elements. There are two types of composite types: array types and record types. 4
SJ 20777—2000
3.44 Concurrentstatement Asynchronous execution of statements, with no defined relative order. Concurrency statements are used to describe data flow structures. 3.45 Configuration configuration
Defines how component instances in a specified block are bound to design entities in order to describe how design entities are combined to form the structure of a complete design.
3. 46 - confom
Two subroutine specifications are considered consistent if, except for certain minor differences, they consist of the same series of lexical elements and the corresponding lexical elements are assigned the same meaning by the availability rules. Consistency is similarly defined for delay constant specifications.
3.47 connection connected
A formal port associated with an actual port or signal. A formal port associated with the reserved word open is considered connected, 3.48 constant constant
An object whose value cannot be changed. A constant can be explicitly declared, a subelement of an explicitly declared constant, or an interface constant. A constant declared in a collection package can also be a delay constant. 3.49 constraint constraint
A subset of a type value. A set of possible values ​​for an object of a specified type that is subject to conditions called constraints. A value is considered to satisfy a constraint if it satisfies the corresponding condition. There are subscript constraints, range constraints, and capacity constraints. 3.50 conversion function a function that converts a value by association. For interface objects of mode in, conversion functions are allowed only in actual parameters. For interface objects of mode ou or 3ffer, conversion functions are allowed only in formal parameters, and for interface objects of mode inout or irkage, conversion functions are allowed in both formal and actual parameters. A conversion function has only one parameter. A conversion function associated with an actual parameter takes the actual parameter type and returns the formal parameter type. A conversion function associated with a formal parameter takes the formal parameter type and returns the actual parameter type 3.51 convertible
property of an operand of a certain type, to which the operand is convertible if an implicit conversion to that type exists.
3.52 current value
a value component that drives a single process, whose time component is not greater than the current simulation time. 3.63 decimal literal
A parabolic literal expressed in decimal notation. The base of the literal is 10. Literals may optionally include exponents or decimal points and fractions.
3.54 deciaration
A structure that defines some declarative entity and associates an identifier (or other symbol) with it. This association is valid within a region of text called the scope of the declaration. Within the scope of the declaration, wherever an identifier can be used to access the associated declarative entity, the identifier is considered to be an abbreviation of the named entity. The abbreviation is considered to express the associated named entity. 3.55 declarative part
A syntactic component of some declaration or statement (e.g., entity declaration, construct, block statement). A declaration part defines a lexical region (usually beginning with a keyword such as is and ending with another keyword such as 3egin). Within this region, declarations may appear. 3.56 declarative region A semantic component of some declaration or statement. The declaration region also includes disjoint parts, such as the declaration region of an entity declaration, which extends to the end of the body of that entity's constructor. 3.57 decorate
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Associates a user-defined attribute with a named entity and defines the value of that attribute. 3.58 default expression default expression A default value used as a formal class, port, or parameter if an interface object is not associated. Default expressions are also used to provide initial values ​​for signals and their drivers.
3.59 deferred constant In a package declaration, a constant is declared without an assignment sign (=) and an expression. The entire declaration of the constant must be present in the package body that defines the constant's value. 3.60 delta cycle A simulation cycle in which the simulation time at the beginning of the cycle is the same as the time at the end of the cycle. That is, simulation time does not advance during a delta cycle, and only non-deferred processes can run hot during a delta cycle. 3.61 expression denote
characteristic of an identifier specified in a declaration. Where the declaration is applicable, the identifier specified in the declaration is considered to denote the named entity declared in the declaration.
3.62 depend(ona libraryunit)A design unit that refers to other library units, either explicitly or implicitly, in a use statement. These dependencies affect the order in which design units are allowed to be compiled.
3.63 depend(on a sigmal value)The character of an implicit signal with respect to some other signal. If R denotes an implicit signal S'Statle(T), S'Quiet(T), or S'Transaction, or if R denotes an implicit GUARD signal and S is any other stable signal named in a guard expression that defines the current value of R, the current value of an implicit signal R is considered to be dependent on the current value of another signal S.
3.64 descending rangeA range that descends from left to right.
3.65 design entitydesign entity
Entity description plus associated constructs. Different design entities may share the same entity description, thus describing different components of a phase interface or different views of the same component. 3.66 design filedesign file
One or more sequential design units. 3.67 design hierarchydesign hierarchyThe complete expression of a design resulting from the successive decomposition of a design entity into subcomponents and binding these subcomponents to other design entities that can be similarly decomposed. 3.68 design library design library
main storage device for the intermediate representation of compiled design units: 3.69 design unit design unit
structure that can be independently compiled and stored in a design library. A design unit can be an entity specification, a construct, a configuration specification, a collection specification or a collection specification 3.70 designate
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property of an access value associated with an object when the access value is non-null. A non-null access value is considered to designate an object 3.71 designated subtype For an access type, a subtype defined by the access type indicates a defined subtype. 3.72 designated type
For an access type, a subtype defined by the access type indicates a base type of a defined subtype. 3.73 designator
a. syntax that forms part of an associated element. A parameter identifier specifies which parameter, port or generic (or sub-element or fragment of a parameter, port or generic) is associated with an actual parameter by specifying an associated element. An actual parameter identifier specifies which actual expression, signal or variable is associated with a formal parameter (a sub-element or sub-element of a formal parameter). An actual parameter identifier may also specify that a parameter in an associated element is an unassociated (open with an actual parameter identifier) ​​formal parameter. b. Identifiers, character literals and operators that define aliases for certain other names. c.abbreviation for a predefined or user-defined attribute in an attribute name or a user-defined attribute in an attribute specification.
d. abbreviation, character literal or operator and possible identification of a named entity in the entity name list in an attribute specification.
e. identifier or operator that defines a subroutine name. 3.74 directly visible a non-selectively available declaration. Except where the declaration is hidden, the declaration is directly available within its scope. A declaration that appears directly in the available part of a collection can be made directly available by means of a use clause. See "available" 3.75 discrete array discrete array
a one-dimensional array whose elements are discrete types. 3.76 discrete range discreterange
a range whose bounds are discrete types.
3.77 discrete type discretetype
an enumerated type or an integer type. Each value of a discrete type has a position number with an integer value. Subscript substitution rules apply to values ​​of discrete types.
3.78 driver driver
Container for the predetermined output waveform of a signal. The value of a signal is a function of the current value of the signal driver. Each process that assigns a value to a specified signal implicitly includes the driver for that signal. Signal assignment statements affect only the associated driver. 3.79 driving value driving value
The value of a signal as a source of other signals. 3.80 effective value effectivevalue
The value obtained by calculating access to a signal within an expression. 3.81 elaboration
The process by which its effect is realized through its declaration. A declaration is not declared until its declaration (including before declaration) is completed. 3.82 element element
Component of a complex type. See "sub-element" for meaning. 3.83 entity declaration entitydeclaration specifies the interface definition between a design entity and the environment in which it is used. It may also specify the declaration and elaboration of parts of the design entity.
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