SJ 20075-1992 Detailed specification for semiconductor integrated circuit Jμ8259A programmable interrupt controller
Some standard content:
Military Standard of Electronic Industry of the People's Republic of China SJ 20075-92
Semiconductor Integrated Circuits
Ju8259A Programmable Interrupt Controller
Detailed Specification
1992-11-19 Issued
Implementation on 1992-05-01
Issued by the Ministry of Machinery and Electronics Industry of the People's Republic of China 1 Specification
1.1 Contents
1.2 Specifications
1.3 Classification…．
2 Reference Documents
3 Requirements
3.1 Detailed Requirements
3.2 Design. Structure and dimensions
3.3 Lead materials and coating
3.4 Electrical characteristics
3.5 Electrical test requirements
3.7 Division of microcircuit groups
4 Quality assurance regulations
Batch samples and inspection
4.3 Identification inspection
4.4 Quality consistency inspection
4.5 Inspection methods
5 Delivery preparation
5.1 Packaging requirements
6 Explanation
6.1 General provisions on test vectors
6.2 Ordering information
6.3 Functional description, symbols and definitions
6.4 Substitution
TYKAONKACa-
People's Republic of China Electronic Industry Military Standard Semiconductor Integrated Circuits
Ju8259A Programmable Interrupt Controller Detailed Specification 1 Scope
1.1 Subject Content
SJ 20075--92
This specification specifies the detailed requirements for the semiconductor integrated circuit Ju8259A programmable interrupt controller (hereinafter referred to as the device).
1.2 Applicable Scope
This specification applies to the development, production and procurement of the device. 1.3 Classification
This specification classifies microcircuits according to device model, device level, package form, rated value and recommended operating conditions. 1.3.1 Device number
The device number shall comply with the provisions of Article 3.6.2 of GJB597 "General Specification for Microcircuits". 1.3.1.1 Device model
The device model is as follows:
Device model
Jμ8259A
1.3.1.2 Device level
Device name
Programmable interrupt controller
The device level shall be Class B as specified in Article 3.4 of GJB597 and Class B1 as specified in this specification. The provisions in this specification that do not specify Class B1 shall be understood as the same as Class B. 1.3.1.3 Packaging form
The packaging forms are as follows:
Packaging form 1
D28L3 (28 dead-line ceramic through-hole package)
C28P3 (ceramic leadless chip carrier package) Note: 1) According to GB7092 "Semiconductor Integrated Circuit Outline Dimensions". 1.3.2 Absolute maximum rated values
The absolute maximum rated values are as follows:
Approved by the Ministry of Machinery and Electronics Industry of the People's Republic of China on November 19, 1992 and implemented on May 1, 1993
Storage temperature range
Voltage at the I terminal relative to the YSS terminal
Non-delay junction temperature (5s)
Junction (7,=125\C)
1.3.3 Recommended operating conditions
The recommended operating conditions are as follows:
Mountain source power
Light inbound level power
Input low voltage output
External charging working temperature specification
Referenced documents
SJ29075—92
Parameter text symbol
GB3431.1—82 Semiconductor integrated circuit text symbol GB3431.2—86 Semiconductor integrated circuit literature symbol Introduction terminal function symbol GB4590—84 Semiconductor integrated circuit mechanical and climatic test methods 3 Flat conductor integrated circuit size
GB7092—93
Microelectronic device test methods and procedures
GJB 548--88
GJB597—88
General specification for microcircuits
GJB105 Electronic product anti-static discharge control manual 3 Requirements
3.1 Detailed requirements
All requirements shall be in accordance with the provisions of GJB597 and this specification. 3.2 Design, structure and dimensions
The design, structure and dimensions shall comply with the provisions of GJB597 and this specification. 3.2.1 Terminal arrangement
The terminal arrangement of the lead should comply with the provisions of Figure 1. The lead terminal is shown in the top view, 2-
TTKAONKAa-
5##3 as shown in #
SJ 20075-—92
Guo IR4
Guo IRI
Zhong AR Feng Feng
Chip carrier package lead arrangement
Figure "Lead arrangement
3.2.2 Function cabinet diagram
The functional block diagram should comply with the provisions of Figure 2.
DO-~D7
Data bus
Buffer
Cascade buffer
Buffer/ratio
Traditional Chinese medicine service||tt| |Register
CASO12
CASI13
V'ss14
16SP/EN
Dual-in-line package pin arrangement
Priority
Resolver
Interrupt mask register
(IMR）
Figure 2 Functional block diagram
China Business Poetry
Register
3.2.3 Functional description, symbols and definitions
SJ 20075—92
Functional description, symbols and definitions shall comply with the provisions of Article 6.3 of this specification. 3.2.4 Package form
The package form shall comply with the provisions of Article 1.3.1.3 of this specification. 3.3 Lead material and coating
Lead material and coating shall comply with the provisions of Article 3.5.6 of GJB597. 3.4 Electrical characteristics
The core characteristics shall comply with the provisions of Table 1: If other provisions are met, they shall be suitable for the full operating temperature range. 3.5 Electrical test requirements
The electrical test requirements for each level of devices shall be the relevant groups specified in Table 2, and the electrical tests of each group shall be in accordance with the provisions of Table 3.
3.6 Marking
The marking shall comply with the provisions of Article 3.6 of GJB597. 3.7 Division of microcircuit groups
The devices involved in this specification are Table 1 Electrical characteristics
Input low level voltage
Input high level voltage
Output low level voltage
Output high level voltage
Interrupt output high level
Input load current
Output impedance time
Electronic current
Output high impedance low level cable
Power supply current
Input capacitance
Input/output capacitance
AU/CS setup time
To RD/INTA+)
RD.INTAT after A0
CS hold time
RD pulse
YoHOINT)
fsu AN-RJ)
Th(RIE-AX)
TwiRLI
Bar price 2
IoL-2.2mA
ToH — -400 μA
TOH--100μA
LOH=-400 μA
,=0 V~ VDD
Vo=0.45 V~VDD
Vo-VpD
Tc=25 °C, VT, =0 V,
FI MH/
Tc=25 °C, VDD =0 V,
Non-test termination Yss
Specification value
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A0.CS setup time
(to WRJ)
WRT active AO/CS
hold time
WR pulse width
data setup write
(to WRt)
WR data hold time
interrupt pulse width
(low voltage)
second or third
INTAI CAS
setup time (duration time from the end of RD to the start of the next
command
WR end to the start of the next
command
data valid time
(start of RDI INTAY
)
RD/ INTA number of posterior
masturbation time
suAH-W)
thWH-AX
fauTVWHy
fh(W-Dx)
SJ 20075—92
Continued Table 1
Condition 3)
tqu(CASV-INTAL)
TarRI-DVy
Ti(RH-DZ)
, when the output is delayed:
IArERH-[NTH)
CAS effective time
(starting from the -th INTA)
)
Charge valid time
(starting from the RD or
INTA\\)
I(INTAL-CASV)
ta(RI-ENL)
Data bus capacitance C is:
Maximum test capacitance 100 pF
Minimum test capacitance 15pF
Sequence number 1)
Allow invalid time
(starting from RDt or
INFA+)
Data valid time
(from valid address
CAS valid to data bus valid time
(RH-ENH
TnAHE-DV
th (CASV-DV)
SJ 20075—92
Continued Table 1
Condition 2)
Data bus capacitance is:
Segment test capacitance 100 pF
Minimum test capacitance 15pF
Note: 1) The sequence of the parameters in this table is consistent with the numbering of the parameters in the timing diagram. 2) If not otherwise specified, Ts = -55 ~ 125 ° C, Vpp = 5 ± 0.5 V, Vss -0 V Table 2 Electrical test requirements
Test requirements
Intermediate (before aging) electrical test
(Method 5004)
Final electrical test \
(Method 5004)
A Test requirements 2)
(Method 5005)
Group B YZAP test
Group C endpoint electrical test
(Method 5005)
Group C inspection added group]
Group D endpoint electrical test
(Method 5005)
A1, A?
B-grade devices
Specification values
Groups (see Table 3)
AI. A2, A3, A7+ A8, A9, A10.An
A1, A2, A3, A4, A7, A8, A9,
Aln,A11
See 4.5.3 of this specification
A2, A3, A8
Not required
A2, A8 (125°C only)
Note: 1) AI, A7 groups require PDA calculation (see 4.2 of this specification) 2) A4 group (C, G:g) is for identification only (see 4.4.1 of this specification). 6
BI grade devices
A1t A2, A3, A7, A9
A1. A2, A3, A4, A7. A9
See 4.5.3 of this specification
A2, A8 (125 °C only)
A2, A8 (125 °C only)
TTKAONKAa-
YOHINT
SJ 20075—92
Table 3A Group Electrical Test
foL -2.2 mA
IoH =-400 μA
foH--100 μA
foH =-400 μA
Vi-0 V~Vpp
Vo =0.45 V~Vpp
Vo-Vep
1Except T-125°C, the parameters, conditions, and specification values are the same as those in Group A1. Except Tc--55C, the parameters, conditions, and specification values are the same as those in Group A1. G
Yop=0 V, FI MHz
Yun=0 V. Termination not tested. Vss
Specification value
According to the provisions of Article 6.2, Te-25°C, functional tests are carried out at Ypp=4.5V and Vpp=5.5V respectively. Except Tc55°℃ and 125°C, they are the same as those in Group A7. FUAH-RLY
th (RH-AX)
Lsu(AH-WLI
hWH-AXI
s(DY-WHI
ThrWH-DX
Fu(CASV-INTAE)
drRL-DV
thrRH-DZ)
dIRH-INTHE
FaINTAL-CASV
Ld(RL-ENL).
LarRH-ENH
thrCASV-DV
The data bus capacitance C is:
Maximum test capacitance 100 pF
Minimum test capacitance 15 pF
SJ 26075—92
Table 3 A group electrical test
Except T-125°℃C, the parameters, conditions and specification values are the same as those of group A9. A11Except Tc--55\C, the parameters, conditions and specification values are the same as those of group A9. Source
Note: (i) RI takes a suitable current limiting resistor:② C1-100 pF+20%:
③VzAP=400V, irrigated at the input end of the device; pulse conversion time (tTLH) ≤5Uns (10%~90%). o
Figure 3 High voltage (Vap) test circuit
Specification value
Connect to the device under test
TYKAOIKAca-
SJ 20075—92
500 ns -
500 ns
Before aging, the following presets must be made:
, the output signal of the 17 terminal,
Note: Observe 12, 13, 15, D7 during the aging process
Figure 4 Aging and life test circuit diagram
Bin address total night
Digital camera bus
RBINTA
Duelin thinks about the wife
Su Mao Zong Lai
SJ20075—92
Test point
Figure 5 AC test input/output waveform
Ci-100 pFt)
Note: 1) C includes the fixture capacitance.
Figure 6 AC test load circuit
Figure 7 Write cycle waveform
Figure 8 Read/INTA timing diagram
TYKAOIKAca-
③VzAP=400V, measured at the input of the device; pulse transition time (tTLH) ≤5Uns (10%~90%). o
Figure 3 High voltage (Vap) test circuit
Specification value
Connect to the device under test
TYKAOIKAca-
SJ 20075—92
500 ns -
500 ns
Before aging, the following presets must be made:
, the output signal of the 17 terminal,
Note: Observe 12, 13, 15, D7 during the aging process
Figure 4 Aging and life test circuit diagram
Bin address total night
Digital camera bus
RBINTA
Duelin thinks about the wife
Su Mao Zong Lai
SJ20075—92
Test point
Figure 5 AC test input/output waveform
Ci-100 pFt)
Note: 1) C includes the fixture capacitance.
Figure 6 AC test load circuit
Figure 7 Write cycle waveform
Figure 8 Read/INTA timing diagram
TYKAOIKAca-
③VzAP=400V, measured at the input of the device; pulse transition time (tTLH) ≤5Uns (10%~90%). o
Figure 3 High voltage (Vap) test circuit
Specification value
Connect to the device under test
TYKAOIKAca-
SJ 20075—92
500 ns -
500 ns
Before aging, the following presets must be made:
, the output signal of the 17 terminal,
Note: Observe 12, 13, 15, D7 during the aging process
Figure 4 Aging and life test circuit diagram
Bin address total night
Digital camera bus
RBINTA
Duelin thinks about the wife
Su Mao Zong Lai
SJ20075—92
Test point
Figure 5 AC test input/output waveform
Ci-100 pFt)
Note: 1) C includes the fixture capacitance.
Figure 6 AC test load circuit
Figure 7 Write cycle waveform
Figure 8 Read/INTA timing diagram
TYKAOIKAca-
③VzAP=400V, measured at the input of the device; pulse transition time (tTLH) ≤5Uns (10%~90%). o
Figure 3 High voltage (Vap) test circuit
Specification value
Connect to the device under test
TYKAOIKAca-
SJ 20075—92
500 ns -
500 ns
Before aging, the following presets must be made:
, the output signal of the 17 terminal,
Note: Observe 12, 13, 15, D7 during the aging process
Figure 4 Aging and life test circuit diagram
Bin address total night
Digital camera bus
RBINTA
Duelin thinks about the wife
Su Mao Zong Lai
SJ20075—92
Test point
Figure 5 AC test input/output waveform
Ci-100 pFt)
Note: 1) C includes the fixture capacitance.
Figure 6 AC test load circuit
Figure 7 Write cycle waveform
Figure 8 Read/INTA timing diagram
TYKAOIKAca-
③VzAP=400V, measured at the input of the device; pulse transition time (tTLH) ≤5Uns (10%~90%). o
Figure 3 High voltage (Vap) test circuit
Specification value
Connect to the device under test
TYKAOIKAca-
SJ 20075—92
500 ns -
500 ns
Before aging, the following presets must be made:
, the output signal of the 17 terminal,
Note: Observe 12, 13, 15, D7 during the aging process
Figure 4 Aging and life test circuit diagram
Bin address total night
Digital camera bus
RBINTA
Duelin thinks about the wife
Su Mao Zong Lai
SJ20075—92
Test point
Figure 5 AC test input/output waveform
Ci-100 pFt)
Note: 1) C includes the fixture capacitance.
Figure 6 AC test load circuit
Figure 7 Write cycle waveform
Figure 8 Read/INTA timing diagram
TYKAOIKAca-5V, Vss-0 VTable 2 Electrical test requirements
Test requirements
Intermediate (before aging) electrical test
(Method 5004)
Final electrical test\
(Method 5004)
A Test requirements 2)
(Method 5005)
Group B YZAP test
Group C endpoint electrical test
(Method 5005)
Group C inspection added group]
Group D endpoint electrical test
(Method 5005)
A1, A?
Class B devices
Specification values
Group (see Table 3)
AI. A2, A3, A7+ A8, A9, A10.An
A1, A2, A3, A4, A7, A8, A9,
Aln,A11
See 4.5.3 of this specification
A2, A3, A8
Not required
A2, A8 (125°C only)
Note: 1) AI, A7 groups require PDA calculation (see 4.2 of this specification) 2) A4 group (C, G:g) is only used for identification (see 4.4.1 of this specification). 6
BI grade devices
A1t A2, A3, A7, A9
A1. A2, A3, A4, A7. A9
See 4.5.3 of this specification
A2, A8 (125 °C only)
A2, A8 (125 °C only)
TTKAONKAa-
YOHINT
SJ 20075—92
Table 3A Group Electrical Test
foL -2.2 mA
IoH =-400 μA
foH--100 μA
foH =-400 μA
Vi-0 V~Vpp
Vo =0.45 V~Vpp
Vo-Vep
1Except T-125°C, the parameters, conditions, and specification values are the same as those in Group A1. Except Tc--55C, the parameters, conditions, and specification values are the same as those in Group A1. G
Yop=0 V, FI MHz
Yun=0 V. Termination not tested. Vss
Specification value
According to the provisions of Article 6.2, Te-25°C, functional tests are carried out at Ypp=4.5V and Vpp=5.5V respectively. Except Tc55°℃ and 125°C, they are the same as those in Group A7. FUAH-RLY
th (RH-AX)
Lsu(AH-WLI
hWH-AXI
s(DY-WHI
ThrWH-DX
Fu(CASV-INTAE)
drRL-DV
thrRH-DZ)
dIRH-INTHE
FaINTAL-CASV
Ld(RL-ENL).
LarRH-ENH
thrCASV-DV
The data bus capacitance C is:
Maximum test capacitance 100 pF
Minimum test capacitance 15 pF
SJ 26075—92
Table 3 A group electrical test
Except T-125°℃C, the parameters, conditions and specification values are the same as those of group A9. A11Except Tc--55\C, the parameters, conditions and specification values are the same as those of group A9. Source
Note: (i) RI takes a suitable current limiting resistor:② C1-100 pF+20%:
③VzAP=400V, irrigated at the input end of the device; pulse conversion time (tTLH) ≤5Uns (10%~90%). o
Figure 3 High voltage (Vap) test circuit
Specification value
Connect to the device under test
TYKAOIKAca-
SJ 20075—92
500 ns -
500 ns
Before aging, the following presets must be made:
, the output signal of the 17 terminal,
Note: Observe 12, 13, 15, D7 during the aging process
Figure 4 Aging and life test circuit diagram
Bin address total night
Digital camera bus
RBINTA
Duelin thinks about the wife
Su Mao Zong Lai
SJ20075—92
Test point
Figure 5 AC test input/output waveform
Ci-100 pFt)
Note: 1) C includes the fixture capacitance.
Figure 6 AC test load circuit
Figure 7 Write cycle waveform
Figure 8 Read/INTA timing diagram
TYKAOIKAca-5V, Vss-0 VTable 2 Electrical test requirements
Test requirements
Intermediate (before aging) electrical test
(Method 5004)
Final electrical test\
(Method 5004)
A Test requirements 2)
(Method 5005)
Group B YZAP test
Group C endpoint electrical test
(Method 5005)
Group C inspection added group]
Group D endpoint electrical test
(Method 5005)
A1, A?
Class B devices
Specification values
Group (see Table 3)
AI. A2, A3, A7+ A8, A9, A10.An
A1, A2, A3, A4, A7, A8, A9,
Aln,A11
See 4.5.3 of this specification
A2, A3, A8
Not required
A2, A8 (125°C only)
Note: 1) AI, A7 groups require PDA calculation (see 4.2 of this specification) 2) A4 group (C, G:g) is only used for identification (see 4.4.1 of this specification). 6
BI grade devices
A1t A2, A3, A7, A9
A1. A2, A3, A4, A7. A9
See 4.5.3 of this specification
A2, A8 (125 °C only)
A2, A8 (125 °C only)
TTKAONKAa-
YOHINT
SJ 20075—92
Table 3A Group Electrical Test
foL -2.2 mA
IoH =-400 μA
foH--100 μA
foH =-400 μA
Vi-0 V~Vpp
Vo =0.45 V~Vpp
Vo-Vep
1Except T-125°C, the parameters, conditions, and specification values are the same as those in Group A1. Except Tc--55C, the parameters, conditions, and specification values are the same as those in Group A1. G
Yop=0 V, FI MHz
Yun=0 V. Termination not tested. Vss
Specification value
According to the provisions of Article 6.2, Te-25°C, functional tests are carried out at Ypp=4.5V and Vpp=5.5V respectively. Except Tc55°℃ and 125°C, they are the same as those in Group A7. FUAH-RLY
th (RH-AX)
Lsu(AH-WLI
hWH-AXI
s(DY-WHI
ThrWH-DX
Fu(CASV-INTAE)
drRL-DV
thrRH-DZ)
dIRH-INTHE
FaINTAL-CASV
Ld(RL-ENL).
LarRH-ENH
thrCASV-DV
The data bus capacitance C is:
Maximum test capacitance 100 pF
Minimum test capacitance 15 pF
SJ 26075—92
Table 3 A group electrical test
Except T-125°℃C, the parameters, conditions and specification values are the same as those of group A9. A11Except Tc--55\C, the parameters, conditions and specification values are the same as those of group A9. Source
Note: (i) RI takes a suitable current limiting resistor:② C1-100 pF+20%:
③VzAP=400V, irrigated at the input end of the device; pulse conversion time (tTLH) ≤5Uns (10%~90%). o
Figure 3 High voltage (Vap) test circuit
Specification value
Connect to the device under test
TYKAOIKAca-
SJ 20075—92
500 ns -
500 ns
Before aging, the following presets must be made:
, the output signal of the 17 terminal,
Note: Observe 12, 13, 15, D7 during the aging process
Figure 4 Aging and life test circuit diagram
Bin address total night
Digital camera busbzxz.net
RBINTA
Duelin thinks about the wife
Su Mao Zong Lai
SJ20075—92
Test point
Figure 5 AC test input/output waveform
Ci-100 pFt)
Note: 1) C includes the fixture capacitance.
Figure 6 AC test load circuit
Figure 7 Write cycle waveform
Figure 8 Read/INTA timing diagram
TYKAOIKAca-
③VzAP=400V, measured at the input of the device; pulse transition time (tTLH) ≤5Uns (10%~90%). o
Figure 3 High voltage (Vap) test circuit
Specification value
Connect to the device under test
TYKAOIKAca-
SJ 20075—92
500 ns -
500 ns
Before aging, the following presets must be made:
, the output signal of the 17 terminal,
Note: Observe 12, 13, 15, D7 during the aging process
Figure 4 Aging and life test circuit diagram
Bin address total night
Digital camera bus
RBINTA
Duelin thinks about the wife
Su Mao Zong Lai
SJ20075—92
Test point
Figure 5 AC test input/output waveform
Ci-100 pFt)
Note: 1) C includes the fixture capacitance.
Figure 6 AC test load circuit
Figure 7 Write cycle waveform
Figure 8 Read/INTA timing diagram
TYKAOIKAca-
③VzAP=400V, measured at the input of the device; pulse transition time (tTLH) ≤5Uns (10%~90%). o
Figure 3 High voltage (Vap) test circuit
Specification value
Connect to the device under test
TYKAOIKAca-
SJ 20075—92
500 ns -
500 ns
Before aging, the following presets must be made:
, the output signal of the 17 terminal,
Note: Observe 12, 13, 15, D7 during the aging process
Figure 4 Aging and life test circuit diagram
Bin address total night
Digital camera bus
RBINTA
Duelin thinks about the wife
Su Mao Zong Lai
SJ20075—92
Test point
Figure 5 AC test input/output waveform
Ci-100 pFt)
Note: 1) C includes the fixture capacitance.
Figure 6 AC test load circuit
Figure 7 Write cycle waveform
Figure 8 Read/INTA timing diagram
TYKAOIKAca-
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