Some standard content:
National Metrology Inspection Regulation of the People's Republic of China JIG 957—2000
Logic Analyzer
Promulgated on December 12, 2000
Implementation on March 1, 2001
Promulgated by the State Administration of Quality and Technical Supervision
JJG957—2UD0
Verification Regulation
for logicanalyzer
LIG 957—2000
This verification regulation was approved by the State Administration of Quality and Technical Supervision on December 12, 2000 and came into force on March 1, 2001.
Responsible unit: National Technical Committee for Non-Fluff Electrical Metrology Drafting unit: Second Institute of 2nd Academy of Aerospace Machinery and Electronics Group This regulation entrusts the National Technical Committee for Radio Metrology to be responsible for the interpretation of this regulation Main drafters:
Han Wenzhong
Canadian drafter:
Sun Jianfeng
JJG957—2000
(Second Institute of 2nd Academy of Aerospace Machinery and Electronics Group) (Second Institute of 2nd Academy of Aerospace Machinery and Electronics Group-Third Institute)
Metrological performance requirements Request
General technical requirements
Appearance and accessories...
Working properly
Basic equipment control
Verification system,
Verification items
Verification equipment
Verification method
Processing of verification results
Verification cycle
Appendix A
Recording format
Appendix B Part Logic Analyzer Technical Specifications
JJG 957—2000
1 Scope
.1IG 957—2000
Logic Analyzer Verification Procedure
This procedure applies to the single verification, subsequent verification and in-use inspection of logic analyzers. 2 Overview
Logic analyzers are divided into timing analysis of logic signals and state analysis of logic signals in principle. Logic analyzers have the characteristics of multiple data channels and multiple synchronous clocks, which can easily analyze the logic timing of digital circuits. Logic analyzers input data signals through multiple logic probes, display data states as logic "1" and "D", can collect data in a multi-level trigger mode, can display test data in a state list mode, and can also display collected data in a waveform mode. Logic analyzers are effective tools for designing, debugging and repairing digital circuits and equipment. 3.1 Maximum clock rate:
Timing analysis: 100MHzt
State analysis: 50MHz:
3.2 Maximum detectable glitch signal width: 0.5n3;3,3 Data setup time: [0~501)ns;3.4 Data hold time: (0~50)
3.5 Threshold level: [-20--+20)V: Maximum allowable error ±3%: 3.6 Minimum clock pulse width: 5154
4 General technical requirements
4.1 Appearance and accessories
The logic analysis instrument should be marked with the manufacturer's name, model, and factory abbreviation. The accessories should be complete, and there should be an instruction manual and the previous calibration certificate. The logic analyzer under test shall be tested and calibrated without any mechanical vibration that may affect the normal operation. 4.2 Normality of operation The logic analyzer under test shall work normally after power-on and pass the test. 5 Control of measuring instruments The control of measuring instruments includes initial test, initial test and in-use test. 5.1 Test conditions 5.1.1 Environmental conditions 1. Ambient temperature: (235°C): L. Relative humidity: not more than 80%; 2. Power supply: (220±10)V, (50±2)Hz: JIG957-20D0 3. Others There shall be no mechanical vibration or electromagnetic interference that may affect the normal operation of the test system. 5.2 Verification Items
The following verification items are common verification items for initial verification, subsequent verification and inspection during use: 5.2.1 Inspection before verification: appearance and accessories, normal working condition: 5.2.2 Maximum clock rate and data establishment and holding time when the clock falling edge acts 5.2.3 Maximum clock rate and data establishment and holding time when the clock rising edge acts; 3.2.4 High clock rate of mixed clock mode during state analysis; 5.2.5 Glitch detection capability;
5.2.6 Input threshold level
5.3 Verification Equipment
5.3.1 Pulse Generator
Should have double-frame output pulse;
Maximum frequency: 50MF
Maximum pulse width: 0.3ns; Maximum allowable error: ±70p8; Input level: (-5-+5) V;
Delay time is adjustable.
3.3.2 Digital oscilloscope
Bandwidth: 500MHz:
Rise time: less than 700F5;
Maximum permissible error of horizontal time base: ±0.1%; 5.3.3 DC voltage source
Output voltage: (-20-120)V
Maximum permissible error: ±0.1%:
The equipment used for verification must be verified by the metrology technical organization and within the validity period. 5.4 Verification method
5.4.1 Pre-verification inspection
5.4.1.1 Appearance and accessories
Check whether the accessories of the logic analyzer are complete, including the instruction manual and the previous inspection certificate. Check whether the logic analyzer has mechanical damage that affects normal operation. 5.4.1.2 Check the band stop
Turn on the power of the logic analyzer and perform self-test. After the self-test is completed, the self-test function pass information should be displayed. If there is a selective function check item, the self-test of the item should be manually sent. Each self-test item should be passed on average. Check whether the interface and touch-change function of the logic analyzer are working properly. 5.4.2 The maximum clock rate and data establishment and retention time when the clock drops and slides 5.4.2.1 Connect the test equipment according to Figure 1 and preheat for 30 minutes. 5.4.2.2 According to the indicator requirements of the logic analyzer to be tested, adjust the waveform output of the pulse generator, and observe the waveform shown in Figure 2 on the ch1 and r2 channels of the digital oscilloscope. 2
Digital oscilloscope
JJG 957.·2000
Logic line new collection
Through the typical charge
Through the negative
T, also analyze the highest clock re-change cycle,: T head
Difference logic analysis only the digital establishment time,
5.4.2.3 Set the working mode of the logic analyzer to state analysis, and open the corresponding channel of the probe under test, input the threshold level to TTL level, adjust the first clock edge to the falling edge trigger, and the logic analyzer data is in hexadecimal mode,
5.4.2.4 Set the display of the logic analyzer to state list mode; start collecting data, follow the logic analysis All lists of the analyzer are displayed as "11\, record the highest clock rate F according to formula (1). (Hz)
Record the data setup time (n);
Record the data hold time 0 (ns).
5,4,2.5 Disconnect the previous clock, connect the next clock end to the core, set the clock as falling edge trigger, repeat step 5.4.2.4, and complete the test for all clocks. 5.4.2.6 Connect the next group of 8-bit data channels, repeat steps 5.4.2.3 to 5.4.2.5, until all data channels are tested.
JJG9572000||t t||5.4.3 The upper opening edge is used as the highest time rate and the number is determined, and the holding time is 5.4.3.1 Connect the test equipment in Figure 1-
According to the index requirements of the tested logic analyzer, adjust the waveform output of the pulse generator according to Figure 3. 3.2
5.4.3.3 Set the working mode of the logic analyzer to state analysis, input the threshold level to TTL level, and turn on the corresponding channel of the probe to be processed, adjust the clock to the upper edge trigger, set the analog calculation to hexadecimal mode,
5.4.3.4 Set the acquisition mode of the reverse logic analyzer to state acquisition mode, and start acquiring data, All tables of the logic analyzer are displayed as "00". Follow the formula [2) Record the highest clock reverse rate (MIz
Record the data establishment time T (s)
Record the data retention time ()
5.4.3.5 Disconnect the previous clock, connect the next clock to the test end, set it to F, replay the steps 5.4.3.4, complete the test at all times or 5.4.3.6 Connect the 7-bit data channel, change the terminal 5.4.3.3 to 5.4.3.5, from the beginning to the end of the test
5.4.4: Status points are new mixed printing clock side or work load high needle connection rate 5.4.4.1 connect two 1 reverse connection test no preparation minutes, 5. *, 4.2 vibration increase detected logic transfer analysis index requirements, dig Figure 4 adjust the waveform output of the impulse, so that T equals T
set the logic load analysis of the working mode is state analysis, mixed pure working state, adjust the main clock of the tube to JJG 957.2000
The first rising edge of the clock is effective, and the operation is completed from the falling edge of the clock. The probe and the response are recorded. The logic analyzer counts to sixteen: 5.1.1.4 Set the logic analyzer to the state of the label list mode and start collecting data. The logic analyzer list should display "0" and "\" alternately. Record the maximum clock rate according to formula (3):
Record data establishment time Tw (n):
Record data image duration (s)
5.4.4.5 Disconnect the clock and connect the next clock to the reverse end. Set the 1 clock as the rising edge of the clock to correct the needle Select the falling edge of the clock, repeat step 5.4.4.4, until all clocks are tested, 5.4.4.6 next group of data channels, repeat steps 5.4.4.3 to 5.4.4.5, until all data channels are tested,
| 5.4.5 Connect the test equipment in Figure 5 and adjust the pulse generator to output the pulse waveform as shown in Figure 6. Note that the pulse generator has no logic analyzer working mode for timing analysis. Open the data under test and put the data into the test port. 957—2000
TTL level, sampling mode is glitch working mode, if the logic analyzer has other setting requirements, it can be set according to the manual:
5.4.5.4 Set the display mode of the logic analyzer to the timing waveform mode, run the logic analyzer, and perform data acquisition.
5.4.5.5 Observe the waveform displayed by the logic analyzer, which should be a normal glitch display. The displayed glitch waveform period is the same as the pulse period. Record (: The glitch detection capability of the logic analyzer is 5.4.5.6. The pulse generator output is connected to the next group of 6-bit data channels, and steps 5.4.5.4 to 5.4.5.5 are repeated until all data probes are tested.
5.4.6 Input threshold level
Connect the calibration equipment according to the figure:
Turn on the positive power source
Logic analyzer
5.4.6.2 Adjust The working state of the entire logic analyzer is timing analysis. Set the corresponding data analyzer to the test head, the acquisition mode, the display is timing waveform mode, and the probe threshold level is user-set mode.
5.4.6.3 Set the probe threshold voltage to 0V5.4.6.4 Set the output voltage of the DC voltage source to the positive limit value Vu of the set threshold voltage5.4.6.5 Run the logic analyzer to start collecting data. The waveform displays all high levels as qualified. Record the positive limit value Ve
Set the output voltage of the DC voltage source to the negative limit value V1 of the set threshold level.3 Run the logic analyzer to start collecting data. The waveform displays all low levels as qualified. Record the negative limit value 5.4.6.7
Set the threshold level of the logic analysis probe to the value of the threshold level range voltage, and then repeat steps 5.4.6.4 and 5.4.6.7.
JIG957—20W
Assume that the threshold voltage of the logic analyzer is the maximum value of the threshold voltage range. 5.4.6.11 Repeat steps 5.4.6.4 to 5.4.6.7, connect the DC voltage source to the next group of 8-bit data probes, and repeat steps 5.4.6.3 to 5.4.6.11.5.4.6.12
Test all data probes
5.5 Processing of verification results
If it meets the technical specifications of the instrument, it is qualified and a verification certificate is issued; if it does not meet the technical specifications of the instrument, it is qualified and a verification failure notice is issued, and the qualified items are indicated. 5.6 Verification period
The verification period of the logic analyzer shall not exceed 1 year, and it can be sent for inspection in advance if necessary. Appendix A
.G 957.2000
Recording format
Clock falling edge effect maximum clock rate I, data setup time T w, hold time C nTable A1
Quotient 8 bits
Quotient 8 bits
Low 8 bits
High 8 bits
Low 8 bits
Quotient 8 bits
Low 8 bits
High 8 bits
Low 8 bits
Clock 2
Clock 3
(MHz)Www.bzxZ.net
!(MHz)
Clock control
Clock rising edge effect maximum clock rate I, data setup time T w, hold time C nTable A1
Quotient 8 bits
Quotient 8 bits
Low 8 bits
High 8 bits
Low 8 bits
Clock 2
Clock 3
(MHz)
!(MHz)
Clock control
Clock rising edge effect maximum clock rate I, data setup time T w, hold time C n ng clock 1
low 8 times
low 8 bits
high you
low 8 bits
commercial 8 depends
low 8 promotion
high 8 bits
keep 8 bits
high 8 bits
clock 2
clock 3- a group of 8-bit data probes, and then repeat steps 5.4.6.3 to 5.4.6.11.5.4.6.12 to test all data probes. 5.5 Processing of calibration results If it meets the technical indicators of the instrument manual, it is qualified and a calibration certificate is issued; if it does not meet the technical indicators of the instrument manual, it is qualified and a calibration failure notice is issued, and the date of the qualified items is indicated. 5.6 Calibration period The calibration cycle of logic analyzer shall not exceed 1 year. It can be inspected in advance if necessary. Appendix A
.G 957.2000
Recording format
Clock falling edge effect maximum clock rate I, data setup time T w, hold time C nTable A1
Quotient 8 bits
Quotient 8 bits
Low 8 bits
High 8 bits
Low 8 bits
Quotient 8 bits
Low 8 bits
High 8 bits
Low 8 bits
Clock 2
Clock 3
(MHz)
!(MHz)
Clock control
Clock rising edge effect maximum clock rate I, data setup time T w, hold time C nTable A1
Quotient 8 bits
Quotient 8 bits
Low 8 bits
High 8 bits
Low 8 bits
Clock 2
Clock 3
(MHz)
!(MHz)
Clock control
Clock rising edge effect maximum clock rate I, data setup time T w, hold time C n ng clock 1
low 8 times
low 8 bits
high you
low 8 bits
commercial 8 depends
low 8 promotion
high 8 bits
keep 8 bits
high 8 bits
clock 2
clock 3- a group of 8-bit data probes, and then repeat steps 5.4.6.3 to 5.4.6.11.5.4.6.12 to test all data probes. 5.5 Processing of calibration results If it meets the technical indicators of the instrument manual, it is qualified and a calibration certificate is issued; if it does not meet the technical indicators of the instrument manual, it is qualified and a calibration failure notice is issued, and the date of the qualified items is indicated. 5.6 Calibration period The calibration cycle of logic analyzer shall not exceed 1 year. It can be inspected in advance if necessary. Appendix A
.G 957.2000
Recording format
Clock falling edge effect maximum clock rate I, data setup time T w, hold time C nTable A1
Quotient 8 bits
Quotient 8 bits
Low 8 bits
High 8 bits
Low 8 bits
Quotient 8 bits
Low 8 bits
High 8 bits
Low 8 bits
Clock 2
Clock 3
(MHz)
!(MHz)
Clock control
Clock rising edge effect maximum clock rate I, data setup time T w, hold time C nTable A1
Quotient 8 bits
Quotient 8 bits
Low 8 bits
High 8 bits
Low 8 bits
Clock 2
Clock 3
(MHz)
!(MHz)
Clock control
Clock rising edge effect maximum clock rate I, data setup time T w, hold time C n ng clock 1
low 8 times
low 8 bits
high you
low 8 bits
commercial 8 depends
low 8 promotion
high 8 bits
keep 8 bits
high 8 bits
clock 2
clock 3
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