Some standard content:
National Standard of the People's Republic of China
8-bit microcomputer STD bus
Standard for an 8-bit
microcomputer bus system, STD bus1 Subject content and scope of application
GB/T 15275-94
This standard provides specifications for the use of 8-bit microprocessors in low-cost modular bus structures. The signals on the bus pass directly from the processor and are buffered but not re-timed. This structure causes some modules to be dependent on the processor. This standard provides the core technical specifications for device-independent parameters. Appendix A to D (reference parts) provide parameters related to various processors. This standard defines the 8-bit microprocessor bus standard that combines small-size modules with large-scale integrated circuit technology, thereby establishing a concept of functional modules and providing a new approach to control-oriented system design. The size, connector and lead pins of the standard module are suitable for bus-type motherboards, which enables any module to be inserted into any slot to work. As shown in Figure 1, the microprocessor controls the functions of the module through the bus interface. The connection of peripheral devices and input/output (I/O) devices is located at the edge of the template (called the user interface). This wiring method forms a regular signal flow from the bus interface through the template to the user interface. Peripheral devices and I/O devices are connected to the system with their own connectors and cables. Complete functions can be added to the system in a modular way by inserting a template with a cable. User interface
Processor
Z80
Address summary
Control bus
General interface
Storage device
State Administration of Technical Supervision 1994-12-D7 approved 2
Digital 1/0
Input interface
Output interface
Industrial 1/0
Photoelectric isolation input
Thyristor
Electrical device
Each device
Figure 1 Bus implementation
Valve coil
Raise the bar 170
DA converter
AD transducer
External solution equipment
Control white
CRT, etc.
External equipment
1995-08-01 implementation
Subject content
Contents specified in this standard:
Template size;
Bus connector:
Bus pin assignment:
Signal definition;
Electrical requirements,
Read/write timing:
Read/write time width parameters.
Contents not specified in this standard:
Template function,
User interface;
cH convertibility;
Motherboard design.
1.2 Applicable scope\
GB/T 15275
5—94
This standard applies to 8-bit microprocessors. The implementation of 16-bit microprocessor buses can also refer to this standard. 1.3 Definition
Assert
Set a signal to a logical "1" state.
Backplane
A printed circuit board including connectors and interconnecting traces. Card
A module composed of a printed circuit board and components. This module can be plugged into the motherboard. Master
The module that controls the transmission of bus signals is the master board, and the motherboard that is controlling the bus is the current motherboard. The module that is in charge of other motherboards is the motherboard. Except for the permanent motherboard, other motherboards are temporary motherboards. Slave
The module that responds to the transmission of bus signals is the slave board. 2 Logic Specifications
2.1 Bus Pin Assignment
The bus pins are arranged into the following five functional groups, as shown in Figure 2. The signal flow is based on the current motherboard, logic power bus:
Data bus:
Address bus:
Control bus:
Auxiliary power bus:
Instructions for use:
1~6 pins
7~14 pins
15~30 pins
31~52 pins
53~~56 pins
:] This article is a supplement to IEEE Std 961 in accordance with GB 1.1. Edit
Control 39
Signal name
D3/A19
D2/A18
D0/A16
REFRESH *
STATLS1*
BUSAK*
INTAK *
WAITRQ*
SYSRESET*
AUX GNT)
Low level valid
2-2 Signal description
Component surface
Signal flow
GB/T15275-94
Logical power supply (-5Vde)
Logical ground
Battery power supply
Input/output
Input/output
Input/output
Data bus/address extension
Address bus
Emit memory or 1/0
/Address selection
Input/output/0 extension
Refresh timing
EPU status
Bus response
Break acknowledge
Wait for request
System reset
Clock from processor
Priority chain output
Auxiliary ground
Auxiliary positive power supply (112Vde)
Signal name
D7/A23
1G/A22
D5/A21
D4/A2
MEMRQ*
MCSYNC*
STATUSO*
BUSRQ*
INTRQ*
NMIRQ*
48PBRESET*
CNTRL*
AUX GND
Figure 2 Bus connector pin assignment
2.2.1 Power bus (pins 1~6 and pins 53~56) Circuit surface
Signal flow
Input/output
Input/output
Logic power supply (-5Vdc)
Logic ground
Logic ground (—5Vde)
Data bus/address extension
Input/output
Input/output
Address bus
Read memory or 1/0||tt ||Memory address selection
Enter/exit memory expansion
KPU machine cycle synchronization
PU status
Line request
Interrupt request
Non-maskable interrupt
Button reset
Auxiliary timing
Priority chain input
Auxiliary ground
Auxiliary negative power supply (-12Vdc)
This dual power bus combines logic power supply and analog power supply, and can provide up to 5 independent power supplies and 2 independent grounds, as shown in Table 1. Independent ground separates the analog line from the digital ground. In practice, all grounds are usually connected to one point at the power supply. 1, 2
Logic power
Digital ground
Backup voltage
GB/T15275—94
Table 1 Power bus pin assignment
Remote logic bias voltage
Auxiliary ground
Auxiliary positive power
Auxiliary negative power
Remote logic power (+5V de)
Remote logic power ground
Battery voltage (+3.5~+5.0v dc)
Low current reverse logic power (-5V de)
Auxiliary power ground
Positive DC excitation (+12V de)
Negative DC power (—12V de)
The logic power on pins 1 and 2 and the digital ground on pins 3 and 4 are required for all templates, and other power pins are optional. 2.2.2 Data bus (pins 7 to 14) (8 bits, bidirectional,3-state, high level active) The direction of the data bus is controlled by the current motherboard and is affected by the read (RD*), write (WR*) and interrupt response (INTAK*) signals.
All templates should release the data bus when not in use, making it in a high impedance state. In response to the bus request (BUSRQ*) input from the temporary motherboard (such as during DMA transfer), the permanent motherboard should release the data bus. When expanding the address, the data bus can be reused. The pin assignment for address expansion should be defined as shown in Figure 2. 2.2.3 Regional bus (pins 15~30) (16 bits, 3-state, high level active) The address is generated by the current motherboard. In response to the bus request (BUSRQ*) input from the temporary motherboard, the permanent motherboard should release the address bus. By reusing 8 additional address bits on the data bus, the address bus can be expanded to 24 bits. The pin assignment for address expansion should be as shown in Figure 2.
The address bus provides 16 address lines for memory or I/O. The memory request (MFMRQ*) and I/O request (I)RQ*> control lines are used to distinguish between these two operations. The number of address lines and how they are used depends on the type of microprocessor, as shown in Table 2. Table 2 Address bus usage examples
Processor type
8080/85
NSC 800
Memory address lines
Number
2.2.4 Control bus (pins 31 to 52)
Address lines during refresh
Lower bits
Lower 8 bits
Number of 1/0 address lines
1/0 matching
Lower 8 bits
Lower 8 bits
Lower 8 bits
Memory matching
The signal lines of the control bus are divided into five parts: memory and I/O control, peripheral device timing, clock and reset, interrupt and bus control to change the serial priority chain.
2. 2. 4. 1 Memory and 1/0 control lines provide signals for basic memory and 1/0 operations. Simple applications may only need the following 6 control signals. All templates should support these 6 memory and I/O control lines. Instructions for use:
11 16.
GB/T 15275-94
31 Pin WR*: Write to memory or output device (3-state, low level valid). WR* is generated by the current motherboard, indicating that the data on the bus will be written to the addressed memory or output device. The selected device should use this signal to write data to the memory or output port. 32 Pin RD*: Read from memory or input device (3-state, low level valid). RD* is generated by the current motherboard, indicating that data is read from memory or input device. The selected input device or memory should use this signal to send data to the data bus.
33 Pin IORQ*: I/O address selection (3-state, low level valid). IORQ* is generated by the current motherboard, indicating whether it is an I/O read or write operation. IORQ* can also be used to control the processor's slave peripherals.
34-pin MEMRQ*: Memory Address Select (3-state, active low). MEMRQ* is generated by the current motherboard to indicate whether it is a memory read or write operation. MEMRQ* can also be used to control the processor's slave peripherals.
35-pin IOEXP: I/O Expansion (3-state, high level to expand, low level to enable). I0EXP is generated by the current motherboard to expand or enable I/O port addressing. The low level active signal should enable the basic (8-bit) I/O address space. The I/O template decodes OEXP. 36-pin MEMEX: Memory Expansion (3-state, high level to expand, low level to enable). MEMEX is generated by the current motherboard to expand or enable memory addressing. The low level active signal should enable the basic (64K) memory address space. The memory template decodes MEMEX. MEMEX can also be used for memory overlay, such as boot operation. The control template can shut down the basic memory and use the replacement memory. 2.2.4.2 Peripheral device timing control lines provide signals to allow microprocessors to use the bus to serve their respective peripheral devices. The 8-bit bus is for any 8-bit microprocessor, but most peripheral devices can only work for a specific microprocessor. There are 4 control lines on the bus for peripheral device timing. These lines have different definitions for different microprocessors, so it allows each microprocessor to support its own peripheral devices (see Table 3 for examples). Templates that require peripheral device timing control lines to provide signals must specifically specify the microprocessor associated with it. Pin 37 REFRESH *: (3-state, low level is valid). REFRESH* is generated by the current motherboard or a separate control template. It is used to refresh dynamic memory. The characteristics and timing relationship of this signal can be a function of the memory or the processor. In systems that do not use the refresh function, this signal can be used as a control signal for any dedicated memory. Systems using static memory can ignore the REFRESH* signal. Pin 38 MCSYNC*: Machine cycle synchronization (3-state, low level is valid). MCSYNC* is generated by the current motherboard. This signal appears once in each machine cycle of the processor. MCSYNC determines the start of the machine cycle. The exact characteristics and timing relationship of this signal depends on the processor. MCSYNC* keeps peripheral devices synchronized with the processor operation. It can also be used to control a bus analyzer that can analyze bus operation on a cycle-by-cycle basis. MCSYNC* can be used to separate multiplexed extended addressing from the data bus. 39-pin STATUS1* Status control line 1 (3-state, low level is valid). STATUS1* is generated by the current motherboard and is used to provide secondary timing for peripheral devices. When STATUS1* is available, it should be used as a signal to identify instruction fetch cycles.
40-pin STATUS0*: Status control line 0 (3-state, low level is valid) 2.2.4.3 Interrupt and bus control lines allow the implementation of bus control schemes such as direct memory access, multi-processor processing, single-stepping, slow memory, power-down restart, and various interrupt modes. For the priority of multiple interrupts or bus requests, serial or parallel priority arbitration schemes can be used.
Processor
NSC800
GB/T15275—94
External device timing control line example
REFRESH*
37 pin
REFRESH*
REFRESH *
Low voltage is almost effective
Business level talk, low level write,
MCSYNG*
38 pin
(RL+WRIINTAK)*
EOUT *($2+)
H(UT+($2 +)
41-pin BUSAK bus response (valid in low power). STATUS1
39-pin
STATUS0*
40-pin
BUSAK* is generated by the Shuijiu mainboard, indicating that the bus can be used by the temporary mainboard. The Shuijiu mainboard should respond to the bus request (BUSRQ*) by releasing the bus and asserting a bus response signal (BUSAK*). BUSAK* is issued after completing the current machine cycle. If multiple controllers want to occupy the bus, this signal must be combined with the priority signal. .42-pin BUSRQ*: Bus request (active low, open collector/drain). BUSRQ* is generated by the temporary master and allows the permanent master to take over the bus operation by releasing all three-state buses. It should release the bus when the current machine cycle is completed. BUSRQ* is used where direct memory access (I>MA) is required. This signal can be input, output or bidirectional, depending on the supported hardware environment. 43-pin [NTAK￥: Interrupt acknowledge (active low). INTAK* is generated by the permanent master to indicate to the device that issued the interrupt that it is ready to respond to the interrupt. For critical interrupts, the device that issued the interrupt should place the vector address on the data bus during INTAK*. If multiple controllers need to access the permanent master, this signal can be used in combination with the priority signal.
44-pin INTRQ*: Interrupt request (active low, open collector/drain). INTRQ* can be generated by any functional slave board to interrupt the processor operation on the permanent master. This signal is best shielded and ignored by the processor unless it has been initiated by software. If the processor accepts the interrupt, it acknowledges it with an INTAK. Other operations depend on the type of processor, the interrupt handling software, and the hardware that supports the interrupt mechanism. 45-pin WAITRQ*: Wait request (active low, open collector/drain). WAITRQ* can be generated by any master or slave board, and it should suspend the operation of the current master board until this signal goes high. The current master board should maintain a valid address state on bus F:. WAITRQ* can be used to insert wait states into processor cycles. For example, slow memory, I/O operations, and single-step operations all use this signal. 46-pin NMIRQ*: Non-screen knock interrupt (active low, open collector/drain). NMIRQ* can be generated by any master or slave board, and this signal is the highest priority interrupt input for the permanent master board. It should be used for emergency signal processing of the processor, such as for power-off indication. 2.2.4.4 Clock and reset lines provide basic clock timing and reset capabilities for the bus. 47-pin SYSRESET*, system reset (active low, collector/drain open) SYSRESET* is generated by any system reset circuit, such as a power-on detection circuit or a push-button reset circuit. All templates that need to initialize the circuit should use SYSRESET*
GB/T 15275-94
48-pin PBRESET*, push-button reset (active low, collector/drain open). PBRESET can be generated by any template and serves as an input to the system reset circuit. 49-pin CLOCK*; clock signal from the permanent motherboard. Cl.OCK* is generated by the permanent motherboard. It is a buffered processor clock signal used for system synchronization as a general clock source. 50-pin CNTRL*: control signal.
CNTRL can be generated by any template and used as a dedicated clock timing. It can be a multiple of the processor clock signal, a real-time clock signal, or an external input signal to the processor. 2.2.4.5 The priority chain signal line is used for serial priority interrupts or bus requests. The specified priority chain is allocated with 2 bus pins, PCI and PCO. Each template participating in the priority chain has logical functions. Templates that do not need the priority chain should short-circuit PCI and PCO on the template. The direction of the priority chain through the template is from pin 52 on the right to pin 51 on the left (from the user interface). Pin 51 PCO: Priority chain output (high level is valid). PCO can be generated by each template, and this signal serves as the PCI input of the next lower priority template on the link. Templates that need priority should keep the PCO on the board low. Pin 52 PCI: Priority chain input (high level is valid). PCI is generated by the PCO of the highest priority template among all templates currently requesting interrupts. When PCI is level, the priority is passed to the template that detects the PCI input. The PCI auxiliary input of the template participating in the priority chain queue should have a pull-up resistor to pull the PCI signal up to +5 V to meet the priority requirements. 3 Timing Specifications
This chapter specifies the timing specifications for operations that are not related to the processor, that is, only the reading and writing of memory and I/O, while the operations related to various processor types are included in Appendix A to D (reference). 3.1 Signal Timing
For the write operation of memory and I/O, the corresponding bus signal timing is specified. The timing of these signals is defined in the bus to ensure the compatibility of each template
3.1.1 Address Selection Signal Timing
Extension signals, address bus signals and request signals are used to select data units in the write operation of memory and I/O. These signals are called address selection signals and are shown in Figure 3. Extension signals (MEMEX, IOEXP) are used to select replacement memory or I/O address space. The address bus signals (A0~A23) are used to uniquely identify the data unit in the memory or I/O space. The request signal (MEMRQ, IO)RQ*) is used to select whether it is a memory operation or an I/O operation. The various address selection signals can appear in any order, and the last signal to appear determines the timing of the signal. All address selection signals must be stable before the memory and I/O read and write operations. (MEMEX)
Body bus
Address selection
(MEMRQ+)
Figure 3 Address selection multiple timing
3.1.2 Read signal timing
GB/T 15275-- 94
As shown in Figure 1, the current card board controls the read timing. The data bus signals are the exception. They are the response to the request from the memory or [/) template. Region: Quick Select
Read (RD-)
Data Bus
Figure 4 Read Signal Timing
The read signal generates a read operation on the selected memory or I/O unit. The read signal should change state during the address select signal, but it may also change at the same time. The trailing edge of the read signal indicates that the data has been transmitted. The read signal always keeps the data bus valid until the motherboard receives the data.
The data bus signal contains the data byte transmitted to the motherboard. These signals remain stable until the read signal is removed: 3.1. 3 Write Signal Timing
As shown in Figure 5, the write timing is controlled by the current motherboard. The address select, data and write signals are all generated by the current motherboard. The data bus signal contains the data byte to be transmitted to the memory or I/O. The data can appear before and after the leading edge of the write value signal. Data should remain stable for a specific period before the trailing edge of the write signal. Data should remain stable for a specific period after the trailing edge of the write signal. Select
Data bus
Write (WR*)
Figure 5 Write signal timing
3.2 Signal time width
The definition of signal time width is to enable users to determine the compatibility of memory templates or I/O templates for read and write operations. 3.2.1 Read timing
Critical read timing is determined by the current motherboard and memory templates or I/O templates. The current motherboard controls the read access time (tARD) and has requirements for the read data setup time (tSRD). The memory or I/O device has a short read access time (1AR) requirement and controls how long the read data is kept on the bus (tHRD). These timing relationships are shown in Figure 6. The compatibility of the module for read operations depends on the comparison between the read access time required by the memory or I/O module and the possible read access time of the motherboard. The IAR of the motherboard should be greater than or equal to the tAR of the memory or I/O module. The motherboard should specify:
tAR--the maximum effective read access time. The IAR value is equal to the minimum value of IARI) minus the minimum address selection
data total
The memory or I/O module should specify:
Figure 6 Critical Read Determination
Required maximum read access time. Since the address selection signal and the read signal may appear at the same time, tAR must specify the read access time under the worst case.
tHRD-
Maximum read data retention time.
GB/T 15275-94
3.2.2 Write Timing
To ensure compatibility, the critical write timing is limited by the write data setup time (tSWD) and write data hold time (tHWD) required by the memory or I/O template, as shown in Figure 7.
The compatibility of the template for write operations depends on the comparison of the write data setup time and hold time required by the memory or I/O template and the possible write data setup and hold time of the motherboard. The tsWD of the motherboard should be greater than or equal to the tSWD of the memory or I/O template. The tHWD of the motherboard should be greater than or equal to the LHWD of the memory or I/O template. The motherboard should specify:
tSWD---minimum possible write data setup time, tHwD-
minimum possible write data hold time.
The memory or I/O template should specify:
tSWD---minimum required write data setup time; tHWD
4 Electrical Specifications
minimum required write data hold time.
Ground Sampling
Data Bus
Rate? Critical Write Timing
This chapter specifies the electrical specifications for CMOS and TTL bus interfaces. Because the threshold characteristics of the two are different, the two types of templates cannot be used on the same motherboard.
4.1CMOS Electrical Specifications
4.1.1Maximum Ratings
The maximum ratings given in Table 4 are the values that should not be exceeded when measured at the template connector pins. These values are not recommended because exceeding these values may damage the devices on the template. 4.1.2CMOS Power Bus Voltage Tolerance
The logic operation of the bus template requires a voltage of +5V. Of course, other voltages listed in Table 5 may also be used on the power bus according to the needs of different template functions and device types. The power signal is measured at the template pins (not at the motherboard connection) and should meet the electrical requirements listed in Table 5.
4.1.3 COMS logic signal characteristicswwW.bzxz.Net
The COMS bus is designed to be compatible with the industry standard high-speed (OMS) logic level. All logic signals should meet the voltage requirements listed in Table 6.
Each template should have only one load for each bus signal. The bus signal driver should preferably meet the wide current requirements listed in Table 6, and the maximum capacitor input load should be 20PF.
The open collector signal should have a 1ka pull-up resistor. The pull-up resistor is best placed on the permanent motherboard. Reference
GB/T 15275-94
Table 4 CMOS Maximum voltage rating
Positive voltage applied to the input or disabled tri-state output Negative voltage applied to the logic input or disabled tri-state output
CMOS power bus voltage rating
Template pin
CMOS parameters
VOH (high level output voltage)
VOL (low level output voltage)
VIH (high level input voltage)
VIL (low level input voltage) Voltage)
4.2 TTL electrical specifications
4.2.1 Maximum ratings
Signal name
Power supply voltage
+3.5V to V.
Table 6 CMOS logic signal voltage ratings
Test conditions
V.=min,1OH=-6mA
V.=min.1OL-6mA
Va-min
V aonin
Reference point
Logic ground (3.4 pin)
Logic ground (3.4 pin)
Test point
Logic ground (3.4 pin)
Remote ground (3.1 pin)
Transparent ground (3.4 pin)
Auxiliary ground (53.51 pin)
Auxiliary ground (53, 54 pin)
The maximum ratings given in Table 7 should not be exceeded when measured at the template connector pins. It is not recommended to use these values. If these values are exceeded, the devices on the template may be damaged. 4.2.2TTL power bus voltage differential
The logic operation of the bus template requires a +5V voltage. Of course, according to the needs of different template functions and device types, other voltages listed in Table 8 may also be used on the power bus. The power signal is measured at the template pins (not at the motherboard connection line) and should meet the requirements of Table 8.
4.2.3TTL logic signal characteristics
TT1. The bus is designed to be compatible with the industry standard TTL logic level. All logic signals should meet the voltage requirements listed in Table 9.
Each module should have only one load for each bus signal. The bus signal driver should preferably meet the current requirements listed in Table 9. The open collector number should have a 4702 pull-up resistor. The pull-up resistor is preferably placed on the permanent motherboard. Table 7 TTL maximum voltage rating
Positive voltage applied to logic input or disabled three-state output Negative voltage limit applied to logic input or disabled three-state output
V. 1 0.5v
Logic ground (3.4 pin)
Logic ground (3.1 pin)
Template pin
CMOS parameters
VOH (high level output voltage)
VOL (low level input voltage)
VIH (high level input voltage)
VIL (low level auxiliary voltage)
4.3 Termination technology
Signal name
ALX +V
GB/T 15275-94
Table 8TT1. Power bus voltage rating
Power supply voltage
+3. 5V to V.
Table 9 TTL logic signal voltage ratings
Test conditions
V..- min,1OH- —3mA
Vr=min,I0L.=24mA
Reference point
Logic ground (3.1 pin)
Logic ground (3.1 pin)
Logic ground (3.1 pin)
Auxiliary ground (53,54 pins)
Auxiliary ground (53,54 pins)
This standard does not specify the termination requirements for the motherboard. The electrical characteristics distributed on the motherboard make them quite suitable for long-distance fast rise and fall time operations. These characteristics are determined by the following factors: the length and layout of the motherboard, the type of connector used, and the number and location of the templates inserted into the motherboard. These characteristics are generally controlled by terminating the signals on the motherboard. A processor running at a low speed can be effectively operated on a short motherboard without terminating a processor running at a high speed and a long motherboard, which requires proper design and termination of the motherboard.
5 Mechanical Specifications
5.1 Template Dimensions
The circuit template shall conform to Figures 9 to 10. and the dimensions given in Table 10. These dimensions do not include the template shoulder and I/O interface connector. If the template does not meet the minimum spacing requirements listed in Table 10, the actual required spacing should be specified. 5.2 Template side profile dimensions
The minimum spacing requirements between boards take into account the following factors: device height, pin solder joint height, clear space between templates, and printed board thickness. Templates designed for minimum spacing should meet the requirements of Table 11. 5.3 Bus connector
The bus connection is achieved through a connector on the edge of the printed circuit board. The connector is matched with 56 pins and 28 pairs on the edge of the template. The distance between the centers of adjacent pins is 3.18 mm (0.125 in). 5.4 Template shoulder
Each template has a single board shoulder installed in the upper right corner, as shown in Figure 9. 5.5 Template positioning
The template is positioned in a certain polarity direction to prevent reverse insertion. The template for polarity positioning should have an offset positioning groove between pins 25 (26) and 27 (28), as shown in Figure 8.
The positioning groove of the template should not be opened between pins 27 (28) and 29 (30) to avoid invalid polarity positioning. Instructions for use:
1) The original text is incorrect,
Template length
Template degree
Including the thickness of the printed circuit board in the plated county
Template spacing
Component height
Component lead solder joint height
Net gap between adjacent templates
1.2710.13mm
05u-0.o05in)
Ding'an sugar
CB/T 15275-94
Table 10 Template size
Nominal value
165.10mm(6.500in)
114.30mm(4.500n)
1.58mm(0.062in)
12. 70mm(0. 500in)
±0.64mm(±0.025in)
+0. 13mm(1 0. bo5in)
0. 64mm(- 0. 025im)
+0.18mm(+0.007in)
0. 08mm( 0. 003in)
- 0. 000mm(—0. 000in)
Table 11 Example of template surface outline size at minimum spacing Minimum
Detail A
(10-390in)
(0.375in）
(0.040in)
25(26)
(28) Deviation calculation
【3h】On the back
Component side
Figure 8 Position and size of the positioning groove for template polarity positioning Minimum
(0.01Qin)
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