This specification specifies the detailed requirements for the semiconductor integrated circuit Jμ82288A type programmable peripheral interface (hereinafter referred to as the device). This specification applies to the development, production and procurement of the device. SJ 20076-1992 Semiconductor Integrated Circuit Jμ82288 Type Bus Controller Detailed Specification SJ20076-1992 Standard download decompression password: www.bzxz.net

Military Standard of the Electronic Industry of the People's Republic of China SJ20076-92
Semiconductor Integrated Circuits
Ju82288 Bus Controller
Detailed Specification
Published on November 19, 1992
Implementation on May 1, 1993
Published by the Ministry of Machinery and Electronics Industry of the People's Republic of China 1 Scope
1.1 Subject Content·
1.2 Applicable Application·
1.3 Classification
2 Reference documents
3 Requirements
3.1 Detailed requirements
3.2 Design, structure and dimensions
3.3 Lead materials and coating.
Electrical test requirements
Division of microcircuit groups
Quality assurance provisions
Sampling and inspection
4.3 Authentication inspection
4.4 Quality consistency inspection
4.5 Inspection methods
5 Delivery preparation
5.1. Packaging requirements ·
6 Notes
6.1 General provisions for sub-test quantity
6.2 Ordering information. ·
6.3 Functional description, symbols and definitions
6.4 Substitution
6.5 Operation
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People's Republic of China Electronic Industry Military Standard Semiconductor Integrated Circuit
Ju82288 Type Bus Controller Detailed Specification
1 Scope
1.1 Subject Content
SJ 20076—92
This specification specifies the detailed maintenance requirements of the semiconductor integrated circuit Ju82288 type bus controller (hereinafter referred to as the device). 1.2 Applicable Scope
This specification is applicable to the development, production and procurement of the device. 1.3 Classification
This specification classifies microcircuits according to device model, device level, package form, rated value and recommended operating conditions. 1.3.1 Device number
The device number shall comply with the provisions of Article 3.6.2 of GJB597 "General Specification for Microcircuits". 1.3.1.1 Device model
The device model is as follows:
Device model
J482288
1.3.1.2 Device level
Device name
Bus controller
The device level is Class B as specified in Article 3.4 of GJB597 and Class B1 as specified in this specification. The provisions in this specification that do not specify Class B1 shall be understood as equivalent to Class B. 1.3.1.3 Package form
The package form is as follows:
Package form\
D20M3 (20-lead porcelain dual (series package)
Note: 1) According to GB7092 "Semiconductor integrated circuit dimensions" 1.3.2 Absolute maximum ratings
The absolute maximum ratings are as follows:
Approved by the Ministry of Machinery and Electronics Industry of the People's Republic of China on November 19, 1992 and implemented on May 1, 1993
The temperature range is used when the output terminal is relative to the Vss terminal of the card
The soldering temperature is (5 s）
Temperature（Te-125°℃)
1.3.3 Recommended.1.Operating conditions
Recommended 1.Operating conditions are as follows:
Power supply battery
Input high level voltage limit
Input level voltage
Case 1.Operating temperature range
Clock 1 time (1.0V to 3.6V)
Clock fall time (3,6V to 1.0 V)
Referenced documents
SJ 20Q76—92
GB3431.1~82 Semiconductor integrated circuit symbols, electrical parameter symbols GB3431.2—86 Semiconductor integrated circuit symbols, functional symbols GB4590—84 Mechanical and climatic test methods for semiconductor integrated circuits GB7092-92 Dimensions of semiconductor integrated circuits GJB548—88 Test methods and procedures for microelectronic devices GJB597—88 General specification for microcircuits
GJB 105 Electronic Products Anti-static Discharge Control Manual 3 Requirements
3.1 Detailed requirements
All requirements shall be in accordance with the provisions of G.IB597 and this specification. 3.2 Design, structure and dimensions
The design, structure and dimensions of the section shall conform to the provisions of GJIB 597 and this specification. 3.2.1 Terminal arrangement
The terminal arrangement shall conform to the provisions of Figure 1. The terminal arrangement is a top view: - 2 -
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3.2.2 Functional block diagram
SJ 20076—92
CMDLY7
CEN/AEN
□INTA
111owc
Figure 1. Terminal arrangement
The functional block diagram should comply with the provisions of Figure 2
Three-state command input
Control input
CEN/AEN
Decoder
Controller
Figure 2 Functional block diagram
+ MWTC
Control input
+ DT/R
→DEN
3.2.3 Functional description, symbols and definitions
SJ 20076--92
Functional description, symbols and definitions shall comply with the provisions of Article 6.3 of this specification. 3.2.4 Package form
The package form shall comply with the provisions of Article 1.3.1.3 of this specification. 3.3 Lead material and coating
Lead material and coating shall comply with the provisions of Section 3.5.6 of GJB597. 3.4 Electrical characteristics
Electrical characteristics shall comply with the provisions of Table 1. If there are no other provisions, they shall be suitable for the full operating range. 3.5 Electrical test requirements
The electrical test requirements for each level of devices shall be the relevant groups specified in Table 2. The electrical tests for each group shall be in accordance with the provisions of Table 3.
3.6 Marking
The marking shall be in accordance with the provisions of Article 36 of GJB597.
3.7 Division of microcircuit groups
The devices involved in this specification are the 107th microcircuit group (see Appendix E of GJB597). Table
Electrical characteristics
Sequence 1)
Clock cycle
Clock high level
Clock low level
Clock rise time
Clock fall time
M/1O and state establishment time
M/TO and state retention time
CENL establishment
CENL retention
READY establishment || tt||Standing time
tsu(ML-CL)
IsurML-CET
iuCL-ML)
th(CL-MHL
fsuiCENLE-CL
Th(CL-CENIH)
su(READYL-CL)
Condition 2)
at 10V
1.0 V to 3.6 V
3.6 V to 1.0 V
Specification value
10,11,
[o,11,
11,12,
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READY hold
time
CMDLY setup
time
CMDLY hold
time
AEN setup
AEN hold
ALE,MCE
valid deactivation time
time (starting from CP
)
ALE,MCE
Invalid delay time
time (starting from CP
)
DEN (write)
Invalid time
(from CENE
DT/R low ground
level time (starting from
CP)
DEN (read)
Valid time
(starting from DTR
)
21DEN (Read)
Invalid delay time
Min (start from CP!
)
tHCL-READYH)
Isu(CMDLYL-CL)
th(CL-CMDLYH)
Esn(AENL-CL)
F(CL-AEN)
Id(CL-ALEH)
tdiCL-MCEH
fa(CL-ALEL)
Ed(CL-MCEl)
Id(CENLL-DENL)
fa(CE-DTL)
La(DTL-DEN1)
Fd(CL-DENL)
$J 2007692
Continued Table 1
Condition 2)
Specification value
Control output load
Ci=100 pF
11,12,
DTRE level
time (from
DEN invalid
start)
Valid delay
H (from MCP
start)
DEN S)
Invalid delay time
time (from CP
DEN valid
time (from
CEN)
DEN valid
time (from
CEN tt||28DEN valid
time (starting from
AEN)
29CMD valid
extended patrol time
(A CP JF
30·CMD effect
Delay time
（From CP
Ia(DENL-DTI)
td(CL-DENH)
FaICL-INE:NL.)
td(CENL-DENL)
+(CINH-DTENH)
Fa(CL-DTH
Id(AENL-DENH)
La(CL-CMDLi
a(CL-CMDH)
SJ20076--92
Continued Table 1
Condition 2）
Current low
Control output load
C=100 pF
Control output load
CL-150 pF
[11,12,
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CMD invalid
learning time (starting from
CEN)
CMI> valid
time (starting from
CEN)
CMD effective
time (starting from
AEN)
CMD floating
delay time
(starting fromAEN
MB construction time
MB holding time
Command invalid
allowed time (starting from
MB+)
Command floating
time (starting fromMB
)
DEN no Valid time
Warning) (starting from MBT
)
DEN valid time
Time (starting from MBI
)
Input low level
Input high levelwwW.bzxz.Net
Clock input low
Level voltage
IdCENE-CMDL)
14[CENII-CMDL.]
Fen(AENL-CMDH)
d(AENH-CMD2)
fau[MBL-CL]
(CL-MBL)
teMMRI. MWTCH)
ta(MBH-MWTC2)
Id(MBH-PENL)
Fa(MHE-DFNH)
YiL(C)
SJ 20076—92
Continued table!
Condition 2
Control wheel load
Ci=IS pF
Control output load
Ci-)s0 pF
Control output load
Ci=100 pf
Clock input high
voltage
input level control
input current
(50 and 31
input terminals)
input leakage current
(all
input terminals except SO and S1)
49output leakage current
50:power supply current
clock input high
input capacitance
input and output capacitance
YrHicy
SJ 2007692
Continued Table 1
Condition 2)
Specification value
Min. Max.
JoL=32mA
lor=16mA
foll--5 mA
IoH=-I mA
0.45 V≤Vg*
f-1 MHz
Note: 1) The parameter numbers in this table are consistent with the parameter numbers in the corresponding waveform diagram. 2) If there is no H, 7c-55~～125°C, Vpp=5+0.5 V, Vss=0 VOMH:
3) AEN is a non-synchronous input. The specification value is for test purposes only to ensure the recognition of a specific clock edge. 4) The output condition only occurs when the output current is an order of magnitude smaller than the output leakage current. 18-
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Test Louqiu
Intermediate (before aging) electrical test
(Method 5004)
Final electrical test 1
(Method 5004)
Group A test fee 2
(Method 5005)
BVZAP test
Group C end point electrical test
(Method 50015)
Group C test additional grouping
D correction end point ratio test
(Method 5005)
-SJ 20076—92
Table 2 Electrical test requirements
Class B devices
A1, A7
A1.A2,A3,A7,A8,49.A10,
A1+ A2: A3, A4, A7, A8, A9,
Al0,All
See Article 4.5.3 of this specification
A2, A3, A8
Not required
A2.A8 (only 125 =C)
Note: 1) A1 and A7 groups require PDA calculation (see Article 4.2 of this specification) 2) A4 group only uses ten identification (see Article 4.4.1 of this specification). Table 3A Group Electrical Test
loL =32 mA
lol.=16 mA
ToH=-5 mA
loH--I mA
0.45V≤VuVDD
B I Level Devices
A1,A2.43,A7,A9
A1; A2, A3;A4 A7: A9
See 4.5.3 of this specification
A2,A8 (125 °C only)
A2、A8 (125 2C only)
Specification A2 Except T=125\C, the parameters, conditions and specification values ​​are grouped with A1. A3 Except Te--55 °C, the parameters, conditions and specification values ​​are grouped with A1.
f-1 MHz
f=1 MHz?
f=1 MHz
.SJ 20076- 92
According to the provisions of Article 6.2, Te=125°C, small performance test is performed at Vpp-4.5V and Vpm-5.5V. Except for 7-55°C and 125°°C, the same grouping as A7, fe
twicL)
guiML-CL)
[(CL-M1
(htL-MHi
sn(CBVI-CI)
thICL-CENLH)
I suH REAYI-CL?
(CE-EAIYH)
fsu(CMDLYI-CL)
+LICI-CMPLYHI
SUAENL-CL||tt| |CL-AENHI
Fa:CI.--ALEHS
tdCL-ME-Hi
Ed(CL-ALELF
JCL-MCELI
Id CENEI-DENLi
fdiCL-DTL
IarDTL-DENHE
faCI.-DENL)
10,11,
11,12,
fIKDENL-DTH).
(aCI-DENIEL
IrCI-DEN1.,
Fe(CENL-IENI!
FaCENIDENH
1.0 V to 3.,6 V
3.6 V to 1.0 V
Control output load
GL =100 pF
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