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Graphic base of electronic elements-IC Graphic

Basic Information

Standard ID: SJ 3181-1989

Standard Name:Graphic base of electronic elements-IC Graphic

Chinese Name: 电子器件图形库-集成电路图形库

Standard category:Electronic Industry Standard (SJ)

state:in force

Date of Release1989-02-10

Date of Implementation:1989-03-01

standard classification number

Standard Classification Number:General>>Standardization Management and General Provisions>>A01 Technical Management

associated standards

Publication information

other information

Introduction to standards:

SJ 3181-1989 Electronic Devices Graphics Library - Integrated Circuit Graphics Library SJ3181-1989 Standard Download Decompression Password: www.bzxz.net



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Ministry of Machinery and Electronics Industry of the People's Republic of China Standard SJ3181-89
Graphic base of electronic elements--IC Graphic
Published on February 10, 1989
Implemented on March 1, 1989
Approved by the Ministry of Machinery and Electronics Industry of the People's Republic of China Ministry of Machinery and Electronics Industry of the People's Republic of China Standard Electronic Components Graphic Library--
Subject Content and Applicable Model Drawings
Integrated Circuit Graphics
SJ3181-89
This standard specifies the design of integrated circuit graphics in the electronic component graphic library for computer-aided design of printed circuit boards Specification.
This standard applies to computer-aided design of printed circuit boards or printed circuit boards designed with the help of computers. Manually designed printed circuit boards can also be used as a reference.
2 Reference standards
GB7092
GB5094
GB2036
3 Terms and codes
"Outline dimensions of semiconductor integrated circuits"
"Project codes in electrical technology"
"Terms and definitions of printed circuits"
3I IC (INTEGRATED CIRCUIT)
Integrated circuit.
32PCB (PRINTED CIRCUIT BOARD)
Printed circuit board is a printed board.
Shape classification name (SHAPESORTINGNAME) is the name for classifying IC according to its appearance.
3.4Sub-class (SUB-TYPE)
The sub-classification after IC is classified according to its appearance is called sub-classification.3.5Span (SPAN)
The distance between the center lines of the two outermost rows of pins of a dual-in-line package.3.6IC model name (TYPENAME)|| tt||That is, IC product model,
3.7 IC logical name (LOGICALNAME)
Logical code of IC in PCB design process: 3.8 Connection node (CONNECTNODE)
Specify the location of connecting IC pin position,
3.9 Text node (TEXTNODE)
The designated point where IC model name and other text are written in IC graphics, approved by the Ministry of Machinery and Electronics Industry of the People's Republic of China on February 10, 1989 and implemented on March 1, 1989
3.10 Pins (PINS)
Lead-out pins of electronic components.
3.11 Land (LAND)
SJ3181-89
Part of the conductive pattern, used to connect or solder components. 3.11.1 Surface layer pads (EXTERNALPADS) Connection pads on the component side and soldering side of PCB.
3.11.2Internal pads (INTERNALPADS) The pads of other conductor layers of a multilayer PCB except for the surface pads. 3.11.3Resist/Solderpads (RESIST/SOLDERPADS) The graphics of the surface layer of a PCB that acts as a solder resist (solder). 311.4Power pattern VOLTAGEPATTERN
The graphics of the pads where the IC pins connected to the power supply are connected to the power supply layer. 3.11.5Ground pattern (GROUNDPATTERN) The graphics of the pads where the IC grounding grid pins are connected to the ground grid layer. 3.11.6Clearance pads (CLEARNCPADS) Graphics where the pins not connected to the power supply or ground grid are isolated from the power supply or ground grid layer. 3.12Silkscreen pattern (SILKSCREENPATTERN) Graphics consisting of the outline diagram of electronic components, model names, and project codes. 3.13Assembly pattern (ASSEMBLYPATTERN) Graphics consisting of the outline diagram of electronic components, model names, and project codes. 3.14 Hole Diagrams (HOLEGRAPHICS)
Aperture and position diagram of IC pins, etc.,
3.15 Logic Layer (LOGICALLAYER)
Logical layering of computer graphics system for operations. 3.16 Conductive Layer (CONDUCTIVELAYER) The surface of the PCB with conductive graphics.
4 IC Graphic Structure
The block diagram of the IC graphic structure is shown in Figure 1
Each IC graphic should include a text description of the IC structure and a graphic representation of the IC in the PCB design. It is also required that the graphics established according to this graphic structure can be converted into physical components through functional assembly. 4.1 IC Structure Description
The left part of Figure 1 specifies the text attributes of the IC structure description, including IC shape classification name, subclass, IC model name, IC logic name, connection node, square node, pin and positioning method. 4.2 Graphical representation of IC in PCB design (shape parameters) The right part of Figure 1 specifies the graphic representation of IC, including silk screen graphics, assembly graphics, connection pads and hole diagrams, etc. 2.—
4.3 Tabular representation of IC graphics
SJ.3181-89
The various parts of the IC graphics in Figure 1 are represented by two tables, Table 1 and Table 2. 4.3.1 Table 1 contains the types and parameters of the hole diagram of the connection pad, 4.3.2 Table 2 contains the text attributes of the IC graphics, silk screen graphics and assembly graphics. 4.3.3 An IC graphic structure parameter should be stored as a graphic element collection in the electronic component graphic library. 5 IC graphic segmentation principles and methods
5.1 Layering principle
Graphic layering should be conducive to library management; it is conducive to data extraction for PCB process and computer-aided testing. 5.2 Layering method
Each conductive layer of the printed circuit board contains many graphic elements with different properties. The computer-aided design system should store these graphic elements separately according to their properties on the logical layer of the system. The logic layer can be divided into the following according to the different types and uses of IC graphics:
device layer (logic layer for device adjustment and positioning); surface layer pad graphic layer:
internal layer connection pad graphic layer:
resistance (helper) welding pad graphic layer;
power supply graphic layer;
f. ground grid graphic layer;
IC logic name layer:
IC model name layer;
compliance symbol wwW.bzxz.Net
silk screen graphic layer:
assembly graphic layer;
k. hole layer:
connection node layer:
text attribute
appearance classification name
mIC pin number layer;
n. other layers.
1 Positioning,
SJ3181-89
IC graphic structure
Silk screen graphic
Positioning mode
Surface layer welding wall
Center positioning
Inner layer welding cake
Shape parameters
Assembly cabinet
Girl assisting girl plate
Figure 1 IC graphic structure block diagram
6 IC graphic structure parameter regulations
The parameters of Table 1 and Table 2 are stipulated item by item as follows: 6.1 Appearance classification name
Common ICs are classified by appearance:||tt| |a. Single in-line package (SINGLEIN-LINEPACKAGE); plate
power supply pattern
ground valve pattern
b. Dual in-line package (DUALIN-LINEPACKAGE), including special staggered shape and double double in-line staggered shape, etc.:
Circular package (CIRCLEPACKAGE)
Grid array type (GRIDARRAY)
6.2 Classification
a, single in-line IC is not subclassified;
J3181---89
b. Dual in-line IC is subclassified by span: c. Ring package IC is subclassified by the number of pins; d. Grid array IC is subclassified by the number of pin rows, 6.3 IC model name
Generally write the specified IC product model. It is the only name in the process of PCB production and management. 6.4 IC logic name
consists of letters and numbers
6.5 Text node position
designers can choose a position with clear sight, and the text should not be re-selected with graphics such as pads. 6.6 Font
can use the computer system's default font or the self-selected font. For the latter, the following are generally used: font height>2.0mm, font width>1.5mm, font line>0.2mm
6.7 Number of pins
total number of IC pins
6.8 Number of columns
6.8.1 For single-row in-line ICs, do not fill in the number of rows (see Table AI). For dual-row in-line ICs, fill in the number of rows according to the actual number of rows (see Table A2-Table A6).
6.8.2 For mesh array ICs, fill in the number of rows in the array (see Table A7).6.9 Pin spacing
Fill in the distance between two adjacent pins in the same row of each type of IC.6.10 Diameter
The diameter of the center of the pin of a circular package IC (see Table A8).6.11 Angle
The angle between two adjacent pins of a circular package IC, expressed in degrees.6.12 Pin numbering
For single-row, dual-row in-line and circular package ICs, the pins are numbered with consecutive positive integers starting from 1; the pin abbreviations of mesh array ICs refer to the regulations of the manufacturer. 6.131 Pins are determined
6.13.1 For single-row in-line ICs, the pin with a straight line on the assembly drawing is pin 1 (see Table A1). 6.13.2 For dual-row in-line ICs, the first pin in the counterclockwise direction from the notch in the assembly drawing is pin 1. The first pin of dual-row staggered and double-row staggered ICs shall be determined according to the manufacturer's regulations (see Table A2-Table A6). 6.13.3 For circular packaged ICs, the first pin in the counterclockwise direction starting from the protrusion in the assembly diagram is pin 1 (see Table A8).
6.13.4 The first pin of mesh array ICs shall be determined in accordance with the manufacturer's regulations. 6.14 Silkscreen pattern
6.14.1 The silkscreen pattern of a single-row in-line IC is represented by a rectangle plus a straight line (see Table A11). 6.14.2 The silkscreen pattern of a dual-row in-line IC is generally represented by a short shape with a square, semicircle or triangle missing 1. 5
SJ3181-89
The length of the rectangle shall not be greater than the actual length of the IC. The width of the rectangle is specified as follows: 2.54mm less than the span for ICs without sockets and 2.54mm greater than the span for ICs with sockets (see Table A3). For dual-row staggered ICs, the width of the silk screen pattern can be drawn according to the actual size (see Table A2 to Table A5). 6.14.3 The silk screen pattern of circular packaged ICs is represented by a circle with a protrusion, and the diameter of the circle is the diameter of the outer contour circle (see Table A8).
6.14.4 The silk screen pattern of mesh array ICs is represented by a square with angled slashes that can cover all pins (see Table A7). 6.15 Assembly Graphics
The assembly graphics regulations for various types of ICs are the same as those for similar ICs. The drawing method of silk screen graphics is similar to that of IC, but the assembly graphics are required to be drawn in proportion to the actual size of the IC. The pins can be represented by \O\, X,, and mouth (see Tables A1 to A8). 6.16 Positioning method of IC graphics
6.16.11 Pin positioning: The position of the IC graphics on the PCB is determined by the position of the first pin as the drawing origin. 6.16.2 Center positioning: The position of the IC graphics on the PCB is determined by the symmetry center of the IC graphics as the drawing origin.
7 The geometric graphics of the connection pads and their matching principles with the wires 7.1 Matching principles
The width of the connection pad, the width of the wire, the gap between the wires, and the gap between the wire and the connection pad should satisfy the following formula: W+(n+1)o+nb
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