GB/T 4728.12-1996 Graphical symbols for electrical schematics Part 12: Binary logic elements
Some standard content:
GB/T4728.12—1996
This standard is a revision of GB4728.12—85 based on IEC617-12:1991 "Graphic Symbols for Electrical Schematics Part 12: Binary Logic Elements", and its technical content and editing format are equivalent to IEC617-12:1991. EC117-15 "Recommended Graphical Symbols Part 15: Binary Logic Elements" in this standard is the predecessor of IEC617-12.
Compared with GB4728.12—85, the main differences between this standard and GB4728.12—85 are as follows: GB4728.12—85 has 5 chapters and 122 articles, including 54 legends and 33 concept diagrams; this standard has 6 chapters and 132 articles, including 127 legends and 48 concept diagrams. The sixth chapter "Complex Function Unit" and its corresponding legends and concept diagrams are mainly added.
Through the revision of this standard, the drawing rules of binary logic element graphic symbols are better unified to meet the needs of international and domestic trade, technology and economic exchanges.
GB4728 "Graphic Symbols for Electrical Diagrams" national standard includes the following 13 parts: 5 General Principles
GB 4728.1—85
GB4728.2—84
GB 4728.3—84
Symbol elements, limiting symbols and other commonly used symbols Wires and connecting devices
GB4728.4—85
Passive components
GB4728.5—85
GB 4728.6—84
GB 4728.7—84
GB4728.8—84
GB 4728.9—85
Semiconductor tubes and electron tubes
Generation and conversion of electric energy
Switches, control and protection devices
Measuring instruments, lamps and signal devices
Telecommunications: switching and peripheral equipment
GB4728.10—85Telecommunications: transmission
GB4728.11-85Electric power, lighting and telecommunications layoutGB/T4728.12—1996Binary logic elementsGB/T4728.13—1996Analog elements
This standard shall be implemented from July 1, 1997, and replace GB4728.12—85. Appendix A and Appendix B of this standard are informative appendices. This standard is proposed by the Ministry of Electronics Industry of the People's Republic of China. This standard is under the jurisdiction of the National Technical Committee for Standardization of Electrical Graphic Symbols. This standard was drafted by: North China Institute of Computing Technology, Standardization Institute of the Ministry of Electronics Industry, Second Institute of Aerospace Industry Corporation, Beijing Broadcasting Equipment Factory, Beijing Dongguang Optoelectronics Factory.
The main drafters of this standard are: Chang Zhenqi, Li Shanzhen, Li Zhanxian, Hu Renyang, Sun Renjie, Zhang Chunting. I
GB/T4728.12—1996
IEC Foreword
1) Formal decisions or agreements on technical issues express the international consensus on the issues discussed as much as possible. The technical committees drafting the documents represent all national committees concerned with these technical issues. 2) These decisions and agreements are in the form of recommended standards for international use and are accepted by national committees in this sense. 3) In order to promote international unification, IEC hopes that national committees, as long as national conditions permit, should try their best to adopt IEC recommended standards as their national standards. Any differences between IEC recommended standards and corresponding national standards should be explained in the corresponding national standards as much as possible.
GB/T4728.12—1996
This international standard was prepared by Working Group 2 of IEC Technical Committee 3A, Subcommittee 3A, Graphical Symbols for Diagrams.
This edition is the second edition of IEC 617-12 and replaces the first edition published in 1983. The contents of this standard are based on the following documents (except the first edition of IEC617-12): June Rule
3A(CO)155
3A(CO)156
3A(CO)157
3A(CO)158
3A(CO)161
3A(CO)162
3A(CO)175
3A(CO)182
3A(CO)855
3A(CO)186
3A(CO)188||tt| |Voting Report
3A(CO)163
3A(CO)164
3A(CO)165
3A(CO)166
3A(CO)173
3A(CO)174
3A(CO)183
3A(CO)195
3A(CO)192
3A(CO)193
3A(CO)194
Full information on the balloting for the approval of this standard can be found in the voting report listed in the table above. This standard refers to the following EC publications:
EC 1082-1 (1991) Preparation of electrical technical documentation Part 1: General rules Graphical symbols for electrical diagrams Part 3: Conductors and connecting devices IEC 617-3 (1983)
IEC 617-13 (1993)
Graphical symbols for electrical diagrams Part 13: Analogue elements V
1 Introduction
National Standard of the People's Republic of China
Graphical symbols for electrical diagrams
Part 12: Binary logic elements
Graphical symbols for electrical diagrams Part 12: Binary logic elements Part 1 General
GB/T 4728.12—1996
idtIEC 617-12:1991
Replaces GB 4728.12—85
This standard specifies the graphic symbols used to represent logical functions. These graphic symbols can also be used to represent physical devices that can perform these logical functions. The symbols are designed with an eye on electrical applications, but most of them can also be used in non-electrical fields, such as pneumatic, hydraulic and mechanical.
2 General instructions
2.1 For the symbols of IEC117-15 "Recommended graphic symbols Part 15: Binary logic elements", the transition period is extended, but they should be gradually replaced by the symbols specified in this standard. The use of other symbols recognized by some national standards, such as those with special shapes, to replace 12-27-01, 12-27-02, 12-27-09, 12-27-10, 12-27-11, 12-27-12, 12-28-01, 12-28-02 and 12-28-04 is not recommended and should not be considered as contradicting this standard. However, it is not allowed to use them to combine complex symbols (for example, as mosaic symbols). 2.2 For the explanation of "logical state" and "logical level", see IEC1082-2 "Functional diagram for the preparation of documents for electrical technology". 2.3 This standard uses the symbols "0" and "1" to represent the two logical states of binary variables. These two states are called "0" state and "1" state.
2.4 A binary variable can be represented by any physical quantity with two different value ranges. In this standard, the physical quantities with these two value ranges are logic levels and are represented by H and L respectively. H is used to represent the logic level with more positive algebraic values, and L is used to represent the logic level with less positive algebraic values. 2.5 If the logic state of a system is represented by other characteristics of physical quantities (for example: positive pulses and negative pulses, pulses and no pulses), these characteristics can still be represented by H and L, or replaced by more appropriate symbols. 3 Explanation of terms
3.1 Internal logic state internallogicstates refers to the logic state assumed to exist at the input or output end within the symbol box. 3.2 External logic states refer to the logic states that are assumed to exist outside the symbol box: a pair of input terminals refers to the logic state before any external qualifying symbol on the input line; a pair of output terminals refers to the logic state after any external qualifying symbol on the output line. Adoption instructions:
1JIEC1082-2 replaces IEC113-7.
Approved by the State Administration of Technical Supervision on December 17, 1996 and implemented on July 1, 1997
3.3 Logic level logic level
GB/T4728.12—1996
refers to the physical quantity conceived to represent a binary variable (see 2.3 and 2.4). Concept diagram
Internal core
External phased state
External logic circuit
Part II
4 Composition of symbols
Symbol structure
4.1 A symbol consists of a box or a combination of boxes and one or more qualifiers. When using a symbol, add input and output lines, and make the best position of the total sample
refer to the line
extract the total limit of the sample position
1 A single asterisk (*) indicates the placement of the qualifier related to the input and output. 2 The total qualifier is not required if and only if the function of the component is completely determined by the qualifier related to the input and output. 4.2 General additional information may be noted in the symbol frame in accordance with the provisions of IEC1082-11. 4.3 Information related to a specific input (output) that is not standardized in the standard may be marked in the square brackets of the corresponding input (output) in the frame and placed after (before) the qualifier of the input (output), as shown in symbol 12-28-14. Additional information related to the overall logical function of the component may be marked in the square brackets in the frame. 4.4 For a component represented by an indivisible symbol, if there are no other relevant qualifiers or marks in the symbol, all its outputs always have the same internal logical state determined by the function of the component. For the basic component frame and qualifier of a redivisible symbol, whether it is expressed in detail or implicitly expressed according to the simplification rules of Section 6.3 of this standard, all outputs of its basic component frame always have the same internal logical state determined by the function of the basic component frame. 4.5 In some figures, some lowercase letters that are not part of the symbol are marked outside the frame. The purpose is only to facilitate the distinction of multiple inputs and outputs when explaining the symbol.
5.1 The aspect ratio of a frame is arbitrary.
5.2 For the combination of frames, see Chapter 6.
Adoption instructions:
1JIEC1082-1 replaces IEC113-7.
12-05-01
12-05-02
12-05-03
6 Application and combination of frames
GB/T4728.12—1996
Graphic symbols
Component frame (square shown)
Common control frame
Common output component frame
6.1 In order to reduce the area required to represent a group of adjacent components, the frames of each component may be adjacent or inlaid according to the following rules. 6.1.1 When the common lines of the component frames are along the direction of information flow, there is no logical connection between these component frames. Concept Diagram
Note: This rule does not necessarily apply to arrays with two or more information flow directions, for example, arrays with multiple information flow directions indicated by common control boxes, common output element boxes, or by associated labels. 6.1.2 If the common line between two boxes is perpendicular to the information flow direction, there is at least one logical connection between them. Since the common control box is not a logical element box, there is no logical connection between the common control box or the common control box, except for those connected to the array and the connection relationship is shown in detail. Each logical connection can be represented by a qualifier marked on one or both sides of the common line. If this method causes confusion in the number of logical connections, the internal connection symbol (symbol 12-08-01) can be used. If there are no qualifiers on both sides of the common line, it can be assumed that there is only one logical connection between the element boxes. Concept Diagram
Each asterisk indicates the position of a qualifier. 6.2 Common control boxes can be connected to related element arrays. Inputs or outputs related to more than one element of the array, or inputs or outputs not related to array elements, can be drawn on the common control box. Such inputs and outputs shall be marked with appropriate labels (if any). 6.2.1 If the input shown in the common control box is the affected input in the associated label (see Chapters 11 and 12), it is only the input common to the elements in the array marked with the input identification number. If the input shown in the common control box is not the affected input in the associated label, it is an input common to all elements in the array or an input that acts on all elements. The common control box is drawn at one end of the array of related elements. Unless otherwise specified, the element adjacent to the common control box is the lowest-order element in the array.
Concept Diagram
6.2.2 Common outputs related to all elements in the array can be shown as the output of the common output element. In the case of an array element with more than one output, a common output element can be used only when these outputs always have the same internal logical state. The use of a common output element means that there is an internal connection from each element of the array to the common output element, but it does not have to be shown. In addition, common output elements may have other inputs, which must be shown in detail. The function of common output elements should be indicated. Each input of a common output element corresponding to an array output has the same internal logical state as that output. Common output element boxes are shown:
in a common control box, or
at the end of an array, or at the opposite position of a common control box if there is one. For an array suitable for having multiple common output element boxes, just draw a double line at one place. Concept diagram
Common output element box in a common
control box
array with two common
input elements
GB/T4728.12—1996
6.3 For arrays composed of several element boxes with the same qualifier, as long as it does not cause confusion, only the qualifier symbol is marked in the first box when drawing. Similarly, when each element frame constituting an array is composed of several identical sub-arrays, only the first sub-array is drawn in detail, and the rest are represented by simple frames. Even if the identification numbers of the associated influencing input (output) and the affected input (output) are different in each element frame of the array, simplification can be achieved (see Chapter 14 for conceptual diagrams). Conceptual diagram
An array of components with the same total limit
Two interconnected arrays
Two interconnected arrays
An array of components with the same limit symbols related to input and output without a common control frame
An array of components with the same limit symbols related to input and output with a common control frame
6.4 In a simplified array composed of several identical component frames, if the function of a lead terminal needs to be represented by connecting two or more lead wires outside the frame, it needs to be shown in detail in the first component frame, and the remaining component frames can be simplified and represented by a single line. The symbols outside the frame that are common to all the connected lead wires should be shown on a single line, while the symbols that are not common can be omitted or shown. 5
Part 3
GB/T4728.12—1996
Conceptual illustration
Qualifying symbols related to input, output and other connections 7 Logical NOT, logical polarity and dynamic input
Each symbol in this chapter is used to determine the relationship between the internal logical state and the external logical state or logic level. If there is no symbol in this chapter at the input or output end, it is assumed that: on the diagram using the logical NOT symbol, the internal logical "1" state corresponds to the external logical "1" state; on the diagram using the logical polarity symbol, the internal logical "1" state corresponds to the logical \H" level. On the diagram using the logical polarity symbol, there is no external logical state. The logical NOT and logical polarity symbols should not be used together on the same diagram, except that logical NOT may appear as an internal connection on the diagram using the logical polarity symbol, see symbol 1 2-08-02 and 12-08-04. 6
12-07-01
12-07-02
12-07-03
12-07-04
12-07 -05
12-07-06
12-07-07
12-07-08
12-07-09
8 internal connection
GB/T4728.12—1996
Logical negation, indicated at the input
Logical negation, indicated at the output
Internal "1" state corresponds to external "0" state Note: The connecting line can extend through the small circle.
Logical polarity indicator, indicated at the input
Logical polarity indicator, indicated at the output
Logical polarity indicator, indicated at the information flow from right to left Input
Logical polarity indicator, indicated at the information flow from right to left Output
Internal "1" state corresponds to the "L" level on the connecting line Dynamic input
Internal "1" state (transient) corresponds to the transition from the external "0" state to the external "1" state. All other times the logical state is "0\
On a diagram using logic polarity symbols, the internal "1" state (transient) corresponds to the transition process from "L" level to "H" level on the wire. All other times the internal logical state is "0\
Dynamic input with logical negation
The internal logical "1" state (transient) corresponds to the transition process from external "1" state to external \0" state. All other times the internal logical state is "0\
Dynamic input with polarity indicator
The internal "1" state (transient) corresponds to the transition process from "H" level to "L" level on the wire. All other times the internal logical state is "0"
The symbols in this chapter are used to determine the relationship between internal connections and internal logical states. Internal connections refer to connections within logic elements. In order to express the logical relationship between components that are combined into blocks, it is useful to use symbols to represent such connections. In most applications, it is also convenient to use the symbols in this item to represent the functions of complex components. In this case, the associated marking should be used to determine the role of the internal input (output). 7
12-08-01
12-08-02
12-08-03
12-08-04
12-08-05
12-08-06
9 Symbols in boxes
-General rules
GB/T4728.12—1996
Internal connections
The internal "1\ state (\0" state) of the input terminal of the right component corresponds to the internal "1" state ("0" state) of the output terminal of the left component
Note: This symbol can be omitted if it does not cause confusion (see 1.2). Internal connection with logical negation
The internal "1" state ("0" state) of the right component input corresponds to the internal "0" state ("1" state) of the left component output
Note: The vertical line can be extended through the small circle.
Internal connection with dynamic characteristics
The internal "1" state (transient state) of the right component input corresponds to the transition process from the internal "0" state to the "1" state of the left component output. At all other times, the internal state of the right component input is "0"
Internal connection with logical negation and dynamic characteristicsThe internal "1" state (transient state) of the right component input corresponds to the transition process from the internal "1" state to the "0" state of the left component outputAt all other times, the internal logical state of the right component input is "0"
Internal input (virtual input)
If this input is not affected by a dominant or corrective association, it is always in its internal "1" stateNote| |tt||, internal inputs and outputs only have internal logical states. 2
Except for symbol 12-07-07, the symbols of Chapter 7 shall not be applied to internal inputs and outputs.
Internal output (virtual output)
The effect of an internal output on the internal input to which it is connected must be indicated with an associated mark
The note to symbol 12-08-05 also applies
9.1 If two or more inputs have the same function qualifier symbol, they are considered to be in an "OR" relationship, except for bidirectional threshold inputs and extended inputs (see symbols 12-09-02 and 12-09-09), in which case the relationship between them should be appropriately indicated. 9.2 Symbols 12-09-13 to 12-09-22 are all It is not a dynamic input. Because the internal logic state determined by the external logic state or level may be affected by other inputs (such as Cm input) and change. If the input represented by symbols 12-09-13 to 12-09-22 has dynamic characteristics, the symbol of 12-07-07 should be added, such as symbol 12-47-01.8
12-09-01
GB/T4728.12—1996
Delayed output
The change of the internal logic state of the output is delayed until the input signal that triggers it to change returns to its starting external logic state or logic level. During the period when the triggering input is in its internal "1" state, any input that affects or is affected by the triggering input The internal logic state of the input must not change, otherwise the output state obtained by the output is not determined by this symbol. If the input signal that causes the change appears at the internal connection, the change of state is delayed until the output of the previous element returns to its starting internal logic state.
If this symbol has no prefix, the output should be considered to be delayed relative to each, +, +, and T inputs and each Cm input or Cm output (see 12-18-01 and 12-18-02); in all other cases, the identification number (or full label when necessary) of all inputs or outputs relative to the delayed output will be shown as a prefix to the symbol, see symbol 12-49-01. To avoid confusion with other symbols, the symbol should be a right angle with two arms of equal length.
For the application and additional explanation of this symbol, see Chapter 41. Concept diagram
If there are no other major inputs, the output changes when the input changes as follows. On a diagram using a logical NOT symbol:
from an external \1\ state to an external \0\ state; from an external “0\ state to an external “1\ state; On a diagram using a polarity indication symbol:
from “H\ level to “1,” level
from \\ voltage to \I\ level2). Internal connection with logical negation
The internal "1" state ("0" state) of the right component input corresponds to the internal "0" state ("1" state) of the left component output
Note: The vertical line can be extended through the small circle.
Internal connection with dynamic characteristics
The internal "1" state (transient state) of the right component input corresponds to the transition process from the internal "0" state to the "1" state of the left component output. At all other times, the internal state of the right component input is "0"
Internal connection with logical negation and dynamic characteristicsThe internal "1" state (transient state) of the right component input corresponds to the transition process from the internal "1" state to the "0" state of the left component outputAt all other times, the internal logical state of the right component input is "0"
Internal input (virtual input)
If the input is not affected by the dominant or corrective relationship, it is always in its internal "1" stateNote| |tt||, internal inputs and outputs only have internal logical states. 2
Except for symbol 12-07-07, the symbols of Chapter 7 shall not be applied to internal inputs and outputs.
Internal output (virtual output)
The effect of an internal output on the internal input to which it is connected must be indicated with an associated mark
The note to symbol 12-08-05 also applies
9.1 If two or more inputs have the same function qualifier symbol, they are considered to be in an "OR" relationship, except for bidirectional threshold inputs and extended inputs (see symbols 12-09-02 and 12-09-09), in which case the relationship between them should be appropriately indicated. 9.2 Symbols 12-09-13 to 12-09-22 are all It is not a dynamic input. Because the internal logic state determined by the external logic state or level may be affected by other inputs (such as Cm input) and change. If the input represented by symbols 12-09-13 to 12-09-22 has dynamic characteristics, the symbol of 12-07-07 should be added, such as symbol 12-47-01.8
12-09-01
GB/T4728.12—1996
Delayed output
The change of the internal logic state of the output is delayed until the input signal that triggers it to change returns to its starting external logic state or logic level. During the period when the triggering input is in its internal "1" state, any input that affects or is affected by the triggering input The internal logic state of the input must not change, otherwise the output state obtained by the output is not determined by this symbol. If the input signal that causes the change appears at the internal connection, the change of state is delayed until the output of the previous element returns to its starting internal logic state.
If this symbol has no prefix, the output should be considered to be delayed relative to each, +, +, and T inputs and each Cm input or Cm output (see 12-18-01 and 12-18-02); in all other cases, the identification number (or full label when necessary) of all inputs or outputs relative to the delayed output will be shown as a prefix to the symbol, see symbol 12-49-01. To avoid confusion with other symbols, the symbol should be a right angle with two arms of equal length.
For the application and additional explanation of this symbol, see Chapter 41. Concept diagram
If there are no other major inputs, the output changes when the input changes as follows. On a diagram using a logical NOT symbol:
from an external \1\ state to an external \0\ state; from an external “0\ state to an external “1\ state; On a diagram using a polarity indication symbol:
from “H\ level to “1,” level
from \\ voltage to \I\ level2). Internal connection with logical negation
The internal "1" state ("0" state) of the right component input corresponds to the internal "0" state ("1" state) of the left component output
Note: The vertical line can be extended through the small circle.
Internal connection with dynamic characteristics
The internal "1" state (transient state) of the right component input corresponds to the transition process from the internal "0" state to the "1" state of the left component output. At all other times, the internal state of the right component input is "0"
Internal connection with logical negation and dynamic characteristicsThe internal "1" state (transient state) of the right component input corresponds to the transition process from the internal "1" state to the "0" state of the left component outputAt all other times, the internal logical state of the right component input is "0"
Internal input (virtual input)
If the input is not affected by the dominant or corrective relationship, it is always in its internal "1" stateNote| |tt||, internal inputs and outputs only have internal logical states. 2
Except for symbol 12-07-07, the symbols of Chapter 7 shall not be applied to internal inputs and outputs.
Internal output (virtual output)
The effect of an internal output on the internal input to which it is connected must be indicated with an associated mark
The note to symbol 12-08-05 also applies
9.1 If two or more inputs have the same function qualifier symbol, they are considered to be in an "OR" relationship, except for bidirectional threshold inputs and extended inputs (see symbols 12-09-02 and 12-09-09), in which case the relationship between them should be appropriately indicated. 9.2 Symbols 12-09-13 to 12-09-22 are all It is not a dynamic input. Because the internal logic state determined by the external logic state or level may be affected by other inputs (such as Cm input) and change. If the input represented by symbols 12-09-13 to 12-09-22 has dynamic characteristics, the symbol of 12-07-07 should be added, such as symbol 12-47-01.8
12-09-01
GB/T4728.12—1996
Delayed output
The change of the internal logic state of the output is delayed until the input signal that triggers it to change returns to its starting external logic state or logic level. During the period when the triggering input is in its internal "1" state, any input that affects or is affected by the triggering input The internal logic state of the input must not change, otherwise the output state obtained by the output is not determined by this symbol. If the input signal that causes the change appears at the internal connection, the change of state is delayed until the output of the previous element returns to its starting internal logic state.
If this symbol has no prefix, the output should be considered to be delayed relative to each, +, +, and T inputs and each Cm input or Cm output (see 12-18-01 and 12-18-02); in all other cases, the identification number (or full label when necessary) of all inputs or outputs relative to the delayed output will be shown as a prefix to the symbol, see symbol 12-49-01. To avoid confusion with other symbols, the symbol should be a right angle with two arms of equal length.
For the application and additional explanation of this symbol, see Chapter 41. Concept diagram
If there are no other major inputs, the output changes when the input changes as follows. On a diagram using a logical NOT symbol:
from an external \1\ state to an external \0\ state; from an external “0\ state to an external “1\ state; On a diagram using a polarity indication symbol: bZxz.net
from “H\ level to “1,” level
from \\ voltage to \I\ level
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