title>Semiconductor discrete device-Detail specification for silicon NPN low power switching transistor of Type 3DK104 - SJ 20057-1992 - Chinese standardNet - bzxz.net
Home > SJ > Semiconductor discrete device-Detail specification for silicon NPN low power switching transistor of Type 3DK104
Semiconductor discrete device-Detail specification for silicon NPN low power switching transistor of Type 3DK104
Basic Information
Standard ID:
SJ 20057-1992
Standard Name:Semiconductor discrete device-Detail specification for silicon NPN low power switching transistor of Type 3DK104
This specification specifies the detailed requirements for 3Dk104 type NPN silicon low power switching transistors (hereinafter referred to as devices); each device provides three levels of product assurance (GP, GT and GCT) in accordance with the provisions of GJB33 "Semiconductor Discrete Device Information Specification". SJ 20057-1992 Semiconductor Discrete Device 3DK104 Type NPN Silicon Low Power Switching Transistor Detailed Specification SJ20057-1992 Standard Download Decompression Password: www.bzxz.net
This specification specifies the detailed requirements for 3Dk104 type NPN silicon low power switching transistors (hereinafter referred to as devices); each device provides three levels of product assurance (GP, GT and GCT) in accordance with the provisions of GJB33 "Semiconductor Discrete Device Information Specification".
GB 4587-1984 Bipolar Transistor Test Methods
GB 7581-1987 Dimensions of Semiconductor Discrete Devices
GJB 33-1985 General Specification for Discrete Semiconductor Devices
GJB 128-1986 Test Methods for Discrete Semiconductor Devices
Some standard content:
1 Scope People's Republic of China Electronic Industry Military Standard Semiconductor Discrete Devices 3DK104 Type NPN Silicon Low Power Switching Transistor Detailed Specification Semiconductor discrcte deviceDetail spceation for silicon NPNlow power switching transistor of type 3DK1041.1 Subject Content SJ20057—92 This specification specifies the detailed requirements for 3DK104 type NPN silicon low power switching transistor (hereinafter referred to as device). Each device provides three levels of product assurance (GP, GT and GCT) in accordance with the provisions of GJB33 "General Specification for Semiconductor Discrete Devices". 1992-11-19 Issued China Electronics Industry Corporation 1993-05-01 Implementation 1.2 Dimensions SJ2005792 The dimensions should conform to the A3-02B type in GB7581 "Dimensions of Discrete Semiconductor Devices" and the following provisions, see Figure 1: Terminal polarity: 1. Emitter 3. Collector Figure 1 Dimensions .0.407 A3-02B 1.3 Maximum Ratings 3DK104A 3DK104B 3DK104C 3DK104D Te-25℃ SJ20057-92 Note: 1) When T>25℃, derate linearly at a rate of 4.0mW/℃. 2) When Tc>25℃, derate linearly at a rate of 15mW/C. 1.4 Main electrical characteristics (T^=25℃) 3DK104A 3DK104B 3DK104C 3DK104D 3DK104A 3DK104B 3DK104C 3DK104D 3DK104A 3DK104B 3DK10 4C 3DK104D Minimum value Maximum value f=30MHz Veg-10V le=50mA Minimum value Maximum value Ie=100mA Ig=10mA Minimum value Maximum value Note: 1) Pulse method (see 4.5.1). hy(Veg=3V) c=10mA Min. Max. f=1MHz Ves=10V Min. Max. Ver(aul le=300mA Ig=30mA Min. Max.|| tt||le=200mA Minimum value Maximum value le=300mA Ig-30mA Minimum value Maximum value Vakaut3 le-100mA Ig=10mA Minimum value Maximum value -65~+200|| tt||le=300mA Minimum value Maximum value lc=300mA Iai=lz30mA Minimum value Maximum value VhE(nngl) le300mA Ig=30mA Minimum value Maximum value Referenced documents|| tt||SJ20057—92 GB4587-84 Test methods for bipolar transistors GB7581—87 7 Dimensions of discrete semiconductor devices GJB33--85 General specification for discrete semiconductor devices GJB128-—86 Test methods for discrete semiconductor devices 3 Requirements 3.1 Details Requirements All requirements shall be in accordance with the provisions of GJB33 and this specification. 3.2 Design, structure and dimensions The design, structure and dimensions of the device shall be in accordance with the provisions of GJB33 and this specification. 3.2.1 Terminal material and coating The terminal material shall be Kovar. The terminal surface coating shall be gold-plated, tin-plated or immersion tin. The selection of terminal material and coating requirements or other requirements shall be clearly specified in the contract or order (see Chapter 6). 3.3 Marking The marking of the device shall be in accordance with the provisions of GJB33. 4 Quality assurance provisions 4.1 Sampling and inspection Sampling and inspection shall be in accordance with the provisions of GJB33 and this specification. 4.2 Qualification inspection Qualification inspection shall be in accordance with the provisions of GJB33. 4.3 Screening (GT and GCT grades only) Screening The selection shall be in accordance with the provisions of GJB33 Table 2 and this specification. The following tests shall be carried out in accordance with this specification Table 1. Devices exceeding the specified limit values shall not be accepted. (See GJB33 Table 2) Intermediate parameter test 8. Power aging Final test 4.3.1 Power aging conditions TA=25±3℃ Vc=30V (3DK104A. C) lcwon and hFes See 4.3.1 Test or experiment Group A2 in Table 1 of this specification; 4/cn=100% of the initial value or 50nA, whichever is greater;Ahrs=±20% of the initial value SJ20056--92 Group A inspection shall be carried out in accordance with the provisions of GJB33 and Table 1 of this specification. 4.4.2 Group B inspection Group B inspection shall be carried out in accordance with the provisions of GJB33 and Table 2 of this specification. The final test and variation (A) requirements shall be carried out in accordance with the steps in Table 4 of this specification. 4.4.3 Group C inspection Group C inspection shall be carried out in accordance with the provisions of GJB33 and Table 3 of this specification. The final test and the change amount (A) requirements shall be carried out according to the steps in Table 4 of this specification. 4.5 Inspection and test methods Inspection and test methods shall be in accordance with the corresponding tables of this specification and the following provisions:4.5.1 Pulse test The pulse test shall be in accordance with the provisions of Article 3.3.2.1 of GJB128. Table 1 Group A inspection Inspection or test Group A1 Appearance and mechanical inspection Group A2 Collector-base breakdown voltage 3DK103B 3DK103C Emitter-base breakdown voltage Collector-emitter breakdown voltage 3DK103B 3DK103 C Collector-emitter breakdown voltage 3DK103B 3DK103C Collector-base cutoff current 3DK103B 3DK103C Emitter-base cutoff current Forward current transfer ratio Forward current transfer ratio Forward current transfer ratio Forward current Transfer ratio Collector-emitter saturation voltage drop GJB128 This specification Appendix A This specification Appendix A GB4587 Emitter-base open circuit le-10μA Collector-base open circuit Ik=10A Emitter-base open circuit||t t||le=100μA Emitter-base open Emitter-base open Ves=30V Vc#=50V Collector-base open Ve,-1V,lc-ImA Vcg=1V.le=-10mA Veg=1V,1c=30mA Ve=1V,le50mA Ic-30mAI-3mA TPD symbol VIRERO Limit value Minimum maximum value VHROCEO VsKCEUe Vegoani Inspection or test Emitter-base cut-off current Forward current transfer ratio Forward current transfer ratio Forward current transfer ratio Collector-emitter saturation voltage drop Collector-emitter saturation voltage drop Base-emitter saturation voltage drop Base-emitter saturation voltage drop A3 group High temperature operation: Collector-base cut-off current||t t||3DK104AC 3DK104B.D Low temperature operation: Forward current transfer ratio A4 group Characteristic frequency Open circuit output capacitance Saturation turn-on time 3DK104A.B 3DK104C, D Saturation turn-off time 3DK1 04A.B 3DK104C.D A5, A6 and A7 grouped Not applicable SJ20057--92 Continued Table 1 GB4587 Collector-base open Vea=5V Vcg=-3V,le-lmA Vc-3V,l-10m A Vc=3Vle=200mA Pulse method (see 4.5.1) Veg=3V.le=300mA Pulse method (see 4.5.1) le=100mAIg=10mA le=300mAl:=30mA Pulse method (see 4.5.1) le =100mAg=10mA le=300mA lg=30mA Pulse method (see 4.5.1) TA=+150C Emitter-base open circuit Ven-80V TA--55C Ve3V.lc-10mA Vcg-10V.le- 50mA f=30MHz Vca-10V.1:=0 lcm300mAl=30mA le=300mA ImIg=30mA LTPD Symbol VerGan Limit Value Minimum Maximum Value Inspection or Test B Group 1 Solderability Durability of marking Group B2 Thermal shock (temperature cycle) a. Fine leak detection b. Coarse leak detection Final test: Group B3 Steady-state working life Final test: Group B4 Visual inspection inside the cap (Design Verification) Bond strength B5 group Not applicable B6 group High temperature life (Not working) Final test: SJ20057-92 Table 2B group inspection GJB128 See Table 4. Steps 1.3 and 4 Vem=30VP u=700mW T-25±3C Device heater or forced air cooling is not allowed See Table 4, steps 2 and 5 Visual inspection standard is as designed during identification TA-200℃ See Table 4, steps 2 and 5 One device per batch, 0 failure 20(C0) C1 grouping Inspection or Test Dimensions Group C2 Thermal shock (glass stress) Terminal strength a. Fine leak detection b. Coarse leak detection Comprehensive temperature/humidity cycle test Appearance and mechanical inspection Final test, Group C3 Variable frequency perturbation Constant acceleration||tt ||Final test, C4 group Salt gas (when applicable) C5 group Not applicable C6 group Steady-state working life Final test: SJ20057—92 Table 3C group inspection GJB128 See Figure 1www.bzxz.net Test condition A||tt ||Test condition E See Table 4. Steps 1.3 and 4 See Table 4, Steps 1, 3 and 4 TA-25±3CVch-30V Pa.=700uw It is not allowed to add heat sink or force air cooling See Table 4. Steps 2 and 5 In=10 Limit value Minimum value Maximum value Inspection or test Collector-base cut-off current 3DK104A.C 3DK104B.D Collector-base cut-off current 3DK104A.C 3DK104B, D Collector-emitter saturation voltage drop Forward current transfer ratio Forward current Transfer ratio SJ20057—92 Table 4 Final test of Group B and Group C CB4587 Emitter-base is open Ven=60V VeB-80V Emitter-base is open Vc#=-60V Von-80V Ic=100mA|| tt||1=10mA Pulse method (see 4.5.1) VeE-3V le=200mA Pulse method (see 4.5.1) Ver=3V le200mA Pulse method (see 4.5.1) Note: 1) For this test, devices exceeding the limit value of Group A shall not be accepted. 5 Delivery preparation Packing requirements shall be in accordance with the provisions of GJB33. 6 Notes Limit value Minimum value Initial value The required terminal materials and coatings shall be specified in the contract or order (see 3.2.1). A1 Purpose SJ20057-92 Appendix A Collector-emitter breakdown voltage test method (supplement) The purpose of this test is to determine whether the breakdown voltage of the transistor is greater than the specified minimum limit under specified conditions. A2 Test circuit The test circuit is shown in Figure A1. Voltage source Collector-emitter breakdown voltage test circuit A3 Steps The current limiting resistor R should be large enough to prevent excessive current from flowing through the transistor and the ammeter. Under the condition of emitter-base open circuit, increase the voltage until the specified test current is reached. If the voltage applied at the specified test current is greater than the minimum limit of V(nRCEO), the transistor is qualified. Additional notes: This specification is proposed by the Science and Technology Quality Bureau of China Electronics Industry Corporation. This specification is under the jurisdiction of China Electronics Technology Standardization Institute. This specification was drafted by China Electronics Technology Standardization Institute and Shijiazhuang Radio Factory No. 2. The main drafters of this specification are: Wang Changfu, Wang Chenglin, and Xie Peilan. Project code: B01014.1). Maximum value of the segment A1 Purpose SJ20057-92 Appendix A Collector-emitter breakdown voltage test method (supplement) The purpose of this test is to determine whether the breakdown voltage of the transistor is greater than the specified minimum limit under specified conditions. A2 Test circuit The test circuit is shown in Figure A1. Voltage source Collector-emitter breakdown voltage test circuit A3 Steps The current limiting resistor R should be large enough to prevent excessive current from flowing through the transistor and the ammeter. Under the condition that the emitter-base is open circuit, increase the voltage until the specified test current is reached. If the voltage applied at the specified test current is greater than the minimum limit of V(nRCEO), the transistor is qualified. Additional notes: This specification is proposed by the Science and Technology Quality Bureau of China Electronics Industry Corporation. This specification is under the jurisdiction of China Electronics Technology Standardization Institute. This specification was drafted by China Electronics Technology Standardization Institute and Shijiazhuang Radio Factory No. 2. The main drafters of this specification are: Wang Changfu, Wang Chenglin, and Xie Peilan. Project code: B01014. Tip: This standard content only shows part of the intercepted content of the complete standard. If you need the complete standard, please go to the top to download the complete standard document for free.